seg71.tan.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt_scan\[0\] cnt_scan\[14\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"cnt_scan\[0\]\" and destination register \"cnt_scan\[14\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.536 ns + Longest register register " "Info: + Longest register to register delay is 2.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_scan\[0\] 1 REG LC_X29_Y20_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y20_N2; Fanout = 3; REG Node = 'cnt_scan\[0\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "" { cnt_scan[0] } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.564 ns) 1.097 ns cnt_scan\[0\]~184 2 COMB LC_X29_Y20_N2 2 " "Info: 2: + IC(0.533 ns) + CELL(0.564 ns) = 1.097 ns; Loc. = LC_X29_Y20_N2; Fanout = 2; COMB Node = 'cnt_scan\[0\]~184'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "1.097 ns" { cnt_scan[0] cnt_scan[0]~184 } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.175 ns cnt_scan\[1\]~180 3 COMB LC_X29_Y20_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.175 ns; Loc. = LC_X29_Y20_N3; Fanout = 2; COMB Node = 'cnt_scan\[1\]~180'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "0.078 ns" { cnt_scan[0]~184 cnt_scan[1]~180 } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.353 ns cnt_scan\[2\]~176 4 COMB LC_X29_Y20_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 1.353 ns; Loc. = LC_X29_Y20_N4; Fanout = 6; COMB Node = 'cnt_scan\[2\]~176'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "0.178 ns" { cnt_scan[1]~180 cnt_scan[2]~176 } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.561 ns cnt_scan\[7\]~156 5 COMB LC_X29_Y20_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.208 ns) = 1.561 ns; Loc. = LC_X29_Y20_N9; Fanout = 6; COMB Node = 'cnt_scan\[7\]~156'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "0.208 ns" { cnt_scan[2]~176 cnt_scan[7]~156 } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.697 ns cnt_scan\[12\]~136 6 COMB LC_X29_Y19_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.697 ns; Loc. = LC_X29_Y19_N4; Fanout = 3; COMB Node = 'cnt_scan\[12\]~136'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "0.136 ns" { cnt_scan[7]~156 cnt_scan[12]~136 } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.536 ns cnt_scan\[14\] 7 REG LC_X29_Y19_N6 17 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 2.536 ns; Loc. = LC_X29_Y19_N6; Fanout = 17; REG Node = 'cnt_scan\[14\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "0.839 ns" { cnt_scan[12]~136 cnt_scan[14] } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.003 ns ( 78.98 % ) " "Info: Total cell delay = 2.003 ns ( 78.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.533 ns ( 21.02 % ) " "Info: Total interconnect delay = 0.533 ns ( 21.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.536 ns" { cnt_scan[0] cnt_scan[0]~184 cnt_scan[1]~180 cnt_scan[2]~176 cnt_scan[7]~156 cnt_scan[12]~136 cnt_scan[14] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.536 ns" { cnt_scan[0] cnt_scan[0]~184 cnt_scan[1]~180 cnt_scan[2]~176 cnt_scan[7]~156 cnt_scan[12]~136 cnt_scan[14] } { 0.000ns 0.533ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "" { clk } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns cnt_scan\[14\] 2 REG LC_X29_Y19_N6 17 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X29_Y19_N6; Fanout = 17; REG Node = 'cnt_scan\[14\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "1.493 ns" { clk cnt_scan[14] } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.962 ns" { clk cnt_scan[14] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt_scan[14] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "" { clk } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns cnt_scan\[0\] 2 REG LC_X29_Y20_N2 3 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X29_Y20_N2; Fanout = 3; REG Node = 'cnt_scan\[0\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "1.493 ns" { clk cnt_scan[0] } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.962 ns" { clk cnt_scan[0] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt_scan[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.962 ns" { clk cnt_scan[14] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt_scan[14] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.962 ns" { clk cnt_scan[0] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt_scan[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.536 ns" { cnt_scan[0] cnt_scan[0]~184 cnt_scan[1]~180 cnt_scan[2]~176 cnt_scan[7]~156 cnt_scan[12]~136 cnt_scan[14] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.536 ns" { cnt_scan[0] cnt_scan[0]~184 cnt_scan[1]~180 cnt_scan[2]~176 cnt_scan[7]~156 cnt_scan[12]~136 cnt_scan[14] } { 0.000ns 0.533ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.962 ns" { clk cnt_scan[14] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt_scan[14] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.962 ns" { clk cnt_scan[0] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt_scan[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "" { cnt_scan[14] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { cnt_scan[14] } {  } {  } } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[6\] cnt_scan\[13\] 9.359 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[6\]\" through register \"cnt_scan\[13\]\" is 9.359 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "" { clk } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns cnt_scan\[13\] 2 REG LC_X29_Y19_N5 17 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X29_Y19_N5; Fanout = 17; REG Node = 'cnt_scan\[13\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "1.493 ns" { clk cnt_scan[13] } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.962 ns" { clk cnt_scan[13] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt_scan[13] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.173 ns + Longest register pin " "Info: + Longest register to pin delay is 6.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_scan\[13\] 1 REG LC_X29_Y19_N5 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y19_N5; Fanout = 17; REG Node = 'cnt_scan\[13\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "" { cnt_scan[13] } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.442 ns) 1.728 ns reduce_or~232 2 COMB LC_X28_Y20_N8 1 " "Info: 2: + IC(1.286 ns) + CELL(0.442 ns) = 1.728 ns; Loc. = LC_X28_Y20_N8; Fanout = 1; COMB Node = 'reduce_or~232'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "1.728 ns" { cnt_scan[13] reduce_or~232 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.337 ns) + CELL(2.108 ns) 6.173 ns dataout\[6\] 3 PIN PIN_214 0 " "Info: 3: + IC(2.337 ns) + CELL(2.108 ns) = 6.173 ns; Loc. = PIN_214; Fanout = 0; PIN Node = 'dataout\[6\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "4.445 ns" { reduce_or~232 dataout[6] } "NODE_NAME" } "" } } { "seg71.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/seg71.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.550 ns ( 41.31 % ) " "Info: Total cell delay = 2.550 ns ( 41.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.623 ns ( 58.69 % ) " "Info: Total interconnect delay = 3.623 ns ( 58.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "6.173 ns" { cnt_scan[13] reduce_or~232 dataout[6] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.173 ns" { cnt_scan[13] reduce_or~232 dataout[6] } { 0.000ns 1.286ns 2.337ns } { 0.000ns 0.442ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "2.962 ns" { clk cnt_scan[13] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt_scan[13] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg71" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/db/seg71.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/接口实验/7段数码管/seg71/" "" "6.173 ns" { cnt_scan[13] reduce_or~232 dataout[6] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "6.173 ns" { cnt_scan[13] reduce_or~232 dataout[6] } { 0.000ns 1.286ns 2.337ns } { 0.000ns 0.442ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}