seg72.map.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 seg72.v(63) " "Warning (10230): Verilog HDL assignment warning at seg72.v(63): truncated value with size 32 to match size of target (4)" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 63 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 seg72.v(71) " "Warning (10230): Verilog HDL assignment warning at seg72.v(71): truncated value with size 32 to match size of target (4)" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 seg72.v(79) " "Warning (10230): Verilog HDL assignment warning at seg72.v(79): truncated value with size 32 to match size of target (4)" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "i seg72.v(42) " "Warning (10240): Verilog HDL Always Construct warning at seg72.v(42): variable \"i\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"i\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 42 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[0\] cnt_scan\[0\] " "Info: Duplicate register \"cnt_digital\[0\]\" merged to single register \"cnt_scan\[0\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[1\] cnt_scan\[1\] " "Info: Duplicate register \"cnt_digital\[1\]\" merged to single register \"cnt_scan\[1\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[2\] cnt_scan\[2\] " "Info: Duplicate register \"cnt_digital\[2\]\" merged to single register \"cnt_scan\[2\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[3\] cnt_scan\[3\] " "Info: Duplicate register \"cnt_digital\[3\]\" merged to single register \"cnt_scan\[3\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[4\] cnt_scan\[4\] " "Info: Duplicate register \"cnt_digital\[4\]\" merged to single register \"cnt_scan\[4\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[5\] cnt_scan\[5\] " "Info: Duplicate register \"cnt_digital\[5\]\" merged to single register \"cnt_scan\[5\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[6\] cnt_scan\[6\] " "Info: Duplicate register \"cnt_digital\[6\]\" merged to single register \"cnt_scan\[6\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[7\] cnt_scan\[7\] " "Info: Duplicate register \"cnt_digital\[7\]\" merged to single register \"cnt_scan\[7\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[8\] cnt_scan\[8\] " "Info: Duplicate register \"cnt_digital\[8\]\" merged to single register \"cnt_scan\[8\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[9\] cnt_scan\[9\] " "Info: Duplicate register \"cnt_digital\[9\]\" merged to single register \"cnt_scan\[9\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[10\] cnt_scan\[10\] " "Info: Duplicate register \"cnt_digital\[10\]\" merged to single register \"cnt_scan\[10\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[11\] cnt_scan\[11\] " "Info: Duplicate register \"cnt_digital\[11\]\" merged to single register \"cnt_scan\[11\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[12\] cnt_scan\[12\] " "Info: Duplicate register \"cnt_digital\[12\]\" merged to single register \"cnt_scan\[12\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[13\] cnt_scan\[13\] " "Info: Duplicate register \"cnt_digital\[13\]\" merged to single register \"cnt_scan\[13\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[14\] cnt_scan\[14\] " "Info: Duplicate register \"cnt_digital\[14\]\" merged to single register \"cnt_scan\[14\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt_digital\[15\] cnt_scan\[15\] " "Info: Duplicate register \"cnt_digital\[15\]\" merged to single register \"cnt_scan\[15\]\"" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 44 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 29 -1 0 } } { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 29 -1 0 } } { "seg72.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/7段数码管/seg72/seg72.v" 29 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "119 " "Info: Implemented 119 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "105 " "Info: Implemented 105 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 16:43:49 2006 " "Info: Processing ended: Fri Oct 20 16:43:49 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}