colorbar.map.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_PERIOD 32'b00000000000000000000001001110100 " "Warning: Can't find a definition for parameter V_PERIOD -- assuming 32'b00000000000000000000001001110100 was intended to be a quoted string" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0 0 "Can't find a definition for parameter %1!s! -- assuming %2!s! was intended to be a quoted string" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_vl vga_vl:inst " "Info: Elaborating entity \"vga_vl\" for hierarchy \"vga_vl:inst\"" {  } { { "../Src/ColorBar.bdf" "inst" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 216 344 480 344 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "H_FRONTPORCH vga_vl.v(75) " "Warning (10036): Verilog HDL or VHDL warning at vga_vl.v(75): object \"H_FRONTPORCH\" assigned a value but never read" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 75 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "H_SYNCTIME vga_vl.v(76) " "Warning (10036): Verilog HDL or VHDL warning at vga_vl.v(76): object \"H_SYNCTIME\" assigned a value but never read" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 76 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "H_BACKPORCH vga_vl.v(77) " "Warning (10036): Verilog HDL or VHDL warning at vga_vl.v(77): object \"H_BACKPORCH\" assigned a value but never read" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 77 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_FRONTPORCH vga_vl.v(83) " "Warning (10036): Verilog HDL or VHDL warning at vga_vl.v(83): object \"V_FRONTPORCH\" assigned a value but never read" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 83 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_SYNCTIME vga_vl.v(84) " "Warning (10036): Verilog HDL or VHDL warning at vga_vl.v(84): object \"V_SYNCTIME\" assigned a value but never read" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 84 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "V_BACKPORCH vga_vl.v(85) " "Warning (10036): Verilog HDL or VHDL warning at vga_vl.v(85): object \"V_BACKPORCH\" assigned a value but never read" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 85 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_vl.v(98) " "Warning (10230): Verilog HDL assignment warning at vga_vl.v(98): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 98 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_vl.v(119) " "Warning (10230): Verilog HDL assignment warning at vga_vl.v(119): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "VGA_PLL.v 1 1 " "Warning: Using design file VGA_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_PLL " "Info: Found entity 1: VGA_PLL" {  } { { "VGA_PLL.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/VGA_PLL.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_PLL VGA_PLL:inst4 " "Info: Elaborating entity \"VGA_PLL\" for hierarchy \"VGA_PLL:inst4\"" {  } { { "../Src/ColorBar.bdf" "inst4" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { -32 336 592 128 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll VGA_PLL:inst4\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"VGA_PLL:inst4\|altpll:altpll_component\"" {  } { { "VGA_PLL.v" "altpll_component" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/VGA_PLL.v" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 104 -1 0 } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 67 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "73 " "Info: Implemented 73 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "65 " "Info: Implemented 65 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 22 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 15:43:05 2006 " "Info: Processing ended: Sat Oct 21 15:43:05 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}