colorbar.hier_info

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

|ColorBar
VGA_HS <= vga_vl:inst.hsync
rst => vga_vl:inst.resetn
clk => VGA_PLL:inst4.inclk0
VGA_VS <= vga_vl:inst.vsync
VGA_RGB[0] <= vga_vl:inst.pixel[0]
VGA_RGB[1] <= vga_vl:inst.pixel[1]
VGA_RGB[2] <= vga_vl:inst.pixel[2]


|ColorBar|vga_vl:inst
resetn => hcnt[9].ACLR
resetn => hcnt[8].ACLR
resetn => hcnt[7].ACLR
resetn => hcnt[6].ACLR
resetn => hcnt[5].ACLR
resetn => hcnt[4].ACLR
resetn => hcnt[3].ACLR
resetn => hcnt[2].ACLR
resetn => hcnt[1].ACLR
resetn => hcnt[0].ACLR
resetn => vsync~reg0.PRESET
resetn => hcnt[10].ACLR
resetn => hsyncint.PRESET
resetn => enable.ACLR
resetn => vcnt[9].ACLR
resetn => vcnt[8].ACLR
resetn => vcnt[7].ACLR
resetn => vcnt[6].ACLR
resetn => vcnt[5].ACLR
resetn => vcnt[4].ACLR
resetn => vcnt[3].ACLR
resetn => vcnt[2].ACLR
resetn => vcnt[1].ACLR
resetn => vcnt[0].ACLR
resetn => vcnt[10].ACLR
clock => hcnt[9].CLK
clock => hcnt[8].CLK
clock => hcnt[7].CLK
clock => hcnt[6].CLK
clock => hcnt[5].CLK
clock => hcnt[4].CLK
clock => hcnt[3].CLK
clock => hcnt[2].CLK
clock => hcnt[1].CLK
clock => hcnt[0].CLK
clock => hsyncint.CLK
clock => enable.CLK
clock => hcnt[10].CLK
orient => pixel~34.OUTPUTSELECT
orient => pixel~35.OUTPUTSELECT
orient => pixel~36.OUTPUTSELECT
hsync <= hsyncint.DB_MAX_OUTPUT_PORT_TYPE
vsync <= vsync~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel[0] <= pixel~39.DB_MAX_OUTPUT_PORT_TYPE
pixel[1] <= pixel~38.DB_MAX_OUTPUT_PORT_TYPE
pixel[2] <= pixel~37.DB_MAX_OUTPUT_PORT_TYPE
blank <= enable.DB_MAX_OUTPUT_PORT_TYPE


|ColorBar|VGA_PLL:inst4
inclk0 => sub_wire4[0].IN1
c0 <= altpll:altpll_component.clk
locked <= altpll:altpll_component.locked


|ColorBar|VGA_PLL:inst4|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= pll.CLK3
clk[4] <= pll.CLK4
clk[5] <= pll.CLK5
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= pll.LOCKED
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>