colorbar.fit.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 15:43:06 2006 " "Info: Processing started: Sat Oct 21 15:43:06 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ColorBar EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"ColorBar\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_TOP" "" "Info: Selected Migration Device List" { { "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_SUB" "EP1C12Q240C8 " "Info: Selected EP1C12Q240C8 for migration" {  } {  } 0 0 "Selected %1!s! for migration" 0 0}  } {  } 0 0 "Selected Migration Device List" 0 0}
{ "Info" "IMPP_MPP_NUM_MIGRATABLE_IO" "227 " "Info: Selected migration device list is legal with 227 total of migratable pins" {  } {  } 0 0 "Selected migration device list is legal with %1!d! total of migratable pins" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "VGA_PLL:inst4\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"VGA_PLL:inst4\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for VGA_PLL:inst4\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "VGA_PLL.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/VGA_PLL.v" 54 -1 0 } } { "../Src/ColorBar.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { -32 336 592 128 "inst4" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFYGR_FYGR_MIGRATION_PIN_CANNOT_BE_USED_AS" "12 regular " "Info: Selected device migration path cannot use 12 pins as \"regular\" I/Os" { { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "80 " "Info: Pin \"80\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "81 " "Info: Pin \"81\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "96 " "Info: Pin \"96\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "97 " "Info: Pin \"97\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "102 " "Info: Pin \"102\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "103 " "Info: Pin \"103\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "198 " "Info: Pin \"198\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "199 " "Info: Pin \"199\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "204 " "Info: Pin \"204\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "205 " "Info: Pin \"205\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "220 " "Info: Pin \"220\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "221 " "Info: Pin \"221\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0}  } {  } 2 0 "Selected device migration path cannot use %1!d! pins as \"%2!s!\" I/Os" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGA_PLL:inst4\|altpll:altpll_component\|_clk0" } { 0 "VGA_PLL:inst4\|altpll:altpll_component\|_clk0" } } } } { "../Src/ColorBar.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { -32 336 592 128 "inst4" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/ColorBar.fld" "" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/ColorBar.fld" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "vga_vl:inst\|hsyncint Global clock " "Info: Automatically promoted some destinations of signal \"vga_vl:inst\|hsyncint\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGA_HS " "Info: Destination \"VGA_HS\" may be non-global or may not use global clock" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 240 608 784 256 "VGA_HS" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 104 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock " "Info: Automatically promoted signal \"rst\" to use Global clock" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 240 104 272 256 "rst" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst " "Info: Pin \"rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 240 104 272 256 "rst" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { rst } "NODE_NAME" } "" } } { "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/ColorBar.fld" "" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/ColorBar.fld" "" "" { rst } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}