colorbar.tan.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 register vga_vl:inst\|vcnt\[10\] register vga_vl:inst\|vcnt\[10\] 1.073 ns " "Info: Minimum slack time is 1.073 ns for clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"vga_vl:inst\|vcnt\[10\]\" and destination register \"vga_vl:inst\|vcnt\[10\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.864 ns + Shortest register register " "Info: + Shortest register to register delay is 0.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|vcnt\[10\] 1 REG LC_X22_Y6_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y6_N5; Fanout = 4; REG Node = 'vga_vl:inst\|vcnt\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.309 ns) 0.864 ns vga_vl:inst\|vcnt\[10\] 2 REG LC_X22_Y6_N5 4 " "Info: 2: + IC(0.555 ns) + CELL(0.309 ns) = 0.864 ns; Loc. = LC_X22_Y6_N5; Fanout = 4; REG Node = 'vga_vl:inst\|vcnt\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "0.864 ns" { vga_vl:inst|vcnt[10] vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 35.76 % ) " "Info: Total cell delay = 0.309 ns ( 35.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.555 ns ( 64.24 % ) " "Info: Total interconnect delay = 0.555 ns ( 64.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "0.864 ns" { vga_vl:inst|vcnt[10] vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.864 ns" { vga_vl:inst|vcnt[10] vga_vl:inst|vcnt[10] } { 0.000ns 0.555ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.615 ns " "Info: + Latch edge is 10.615 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns 10.615 ns inverted 50 " "Info: Clock period of Destination clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with inverted offset of 10.615 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 10.615 ns " "Info: - Launch edge is 10.615 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns 10.615 ns inverted 50 " "Info: Clock period of Source clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with inverted offset of 10.615 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 destination 7.518 ns + Longest register " "Info: + Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to destination register is 7.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns vga_vl:inst\|hsyncint 2 REG LC_X21_Y10_N2 13 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X21_Y10_N2; Fanout = 13; REG Node = 'vga_vl:inst\|hsyncint'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.609 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.198 ns) + CELL(0.711 ns) 7.518 ns vga_vl:inst\|vcnt\[10\] 3 REG LC_X22_Y6_N5 4 " "Info: 3: + IC(4.198 ns) + CELL(0.711 ns) = 7.518 ns; Loc. = LC_X22_Y6_N5; Fanout = 4; REG Node = 'vga_vl:inst\|vcnt\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "4.909 ns" { vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 21.89 % ) " "Info: Total cell delay = 1.646 ns ( 21.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.872 ns ( 78.11 % ) " "Info: Total interconnect delay = 5.872 ns ( 78.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 7.518 ns - Shortest register " "Info: - Shortest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 7.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns vga_vl:inst\|hsyncint 2 REG LC_X21_Y10_N2 13 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X21_Y10_N2; Fanout = 13; REG Node = 'vga_vl:inst\|hsyncint'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.609 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.198 ns) + CELL(0.711 ns) 7.518 ns vga_vl:inst\|vcnt\[10\] 3 REG LC_X22_Y6_N5 4 " "Info: 3: + IC(4.198 ns) + CELL(0.711 ns) = 7.518 ns; Loc. = LC_X22_Y6_N5; Fanout = 4; REG Node = 'vga_vl:inst\|vcnt\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "4.909 ns" { vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 21.89 % ) " "Info: Total cell delay = 1.646 ns ( 21.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.872 ns ( 78.11 % ) " "Info: Total interconnect delay = 5.872 ns ( 78.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "0.864 ns" { vga_vl:inst|vcnt[10] vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.864 ns" { vga_vl:inst|vcnt[10] vga_vl:inst|vcnt[10] } { 0.000ns 0.555ns } { 0.000ns 0.309ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[10] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk VGA_RGB\[0\] vga_vl:inst\|hcnt\[3\] 11.985 ns register " "Info: tco from clock \"clk\" to destination pin \"VGA_RGB\[0\]\" through register \"vga_vl:inst\|hcnt\[3\]\" is 11.985 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk VGA_PLL:inst4\|altpll:altpll_component\|_clk0 -1.885 ns + " "Info: + Offset between input clock \"clk\" and output clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is -1.885 ns" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 24 104 272 40 "clk" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 2.385 ns + Longest register " "Info: + Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 2.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.711 ns) 2.385 ns vga_vl:inst\|hcnt\[3\] 2 REG LC_X21_Y10_N8 9 " "Info: 2: + IC(1.674 ns) + CELL(0.711 ns) = 2.385 ns; Loc. = LC_X21_Y10_N8; Fanout = 9; REG Node = 'vga_vl:inst\|hcnt\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.385 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[3] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.81 % ) " "Info: Total cell delay = 0.711 ns ( 29.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 70.19 % ) " "Info: Total interconnect delay = 1.674 ns ( 70.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.385 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.385 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[3] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 95 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.261 ns + Longest register pin " "Info: + Longest register to pin delay is 11.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|hcnt\[3\] 1 REG LC_X21_Y10_N8 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y10_N8; Fanout = 9; REG Node = 'vga_vl:inst\|hcnt\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { vga_vl:inst|hcnt[3] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.442 ns) 1.721 ns vga_vl:inst\|LessThan~1901 2 COMB LC_X21_Y9_N7 2 " "Info: 2: + IC(1.279 ns) + CELL(0.442 ns) = 1.721 ns; Loc. = LC_X21_Y9_N7; Fanout = 2; COMB Node = 'vga_vl:inst\|LessThan~1901'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "1.721 ns" { vga_vl:inst|hcnt[3] vga_vl:inst|LessThan~1901 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.442 ns) 2.851 ns vga_vl:inst\|LessThan~1902 3 COMB LC_X22_Y9_N8 2 " "Info: 3: + IC(0.688 ns) + CELL(0.442 ns) = 2.851 ns; Loc. = LC_X22_Y9_N8; Fanout = 2; COMB Node = 'vga_vl:inst\|LessThan~1902'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "1.130 ns" { vga_vl:inst|LessThan~1901 vga_vl:inst|LessThan~1902 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(0.442 ns) 4.537 ns vga_vl:inst\|pixel\[0\]~1279 4 COMB LC_X21_Y8_N2 1 " "Info: 4: + IC(1.244 ns) + CELL(0.442 ns) = 4.537 ns; Loc. = LC_X21_Y8_N2; Fanout = 1; COMB Node = 'vga_vl:inst\|pixel\[0\]~1279'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "1.686 ns" { vga_vl:inst|LessThan~1902 vga_vl:inst|pixel[0]~1279 } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.569 ns) + CELL(0.292 ns) 6.398 ns vga_vl:inst\|pixel\[0\]~1283 5 COMB LC_X22_Y9_N2 1 " "Info: 5: + IC(1.569 ns) + CELL(0.292 ns) = 6.398 ns; Loc. = LC_X22_Y9_N2; Fanout = 1; COMB Node = 'vga_vl:inst\|pixel\[0\]~1283'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "1.861 ns" { vga_vl:inst|pixel[0]~1279 vga_vl:inst|pixel[0]~1283 } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.739 ns) + CELL(2.124 ns) 11.261 ns VGA_RGB\[0\] 6 PIN PIN_159 0 " "Info: 6: + IC(2.739 ns) + CELL(2.124 ns) = 11.261 ns; Loc. = PIN_159; Fanout = 0; PIN Node = 'VGA_RGB\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "4.863 ns" { vga_vl:inst|pixel[0]~1283 VGA_RGB[0] } "NODE_NAME" } "" } } { "../Src/ColorBar.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Src/ColorBar.bdf" { { 288 608 784 304 "VGA_RGB\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.742 ns ( 33.23 % ) " "Info: Total cell delay = 3.742 ns ( 33.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.519 ns ( 66.77 % ) " "Info: Total interconnect delay = 7.519 ns ( 66.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "11.261 ns" { vga_vl:inst|hcnt[3] vga_vl:inst|LessThan~1901 vga_vl:inst|LessThan~1902 vga_vl:inst|pixel[0]~1279 vga_vl:inst|pixel[0]~1283 VGA_RGB[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.261 ns" { vga_vl:inst|hcnt[3] vga_vl:inst|LessThan~1901 vga_vl:inst|LessThan~1902 vga_vl:inst|pixel[0]~1279 vga_vl:inst|pixel[0]~1283 VGA_RGB[0] } { 0.000ns 1.279ns 0.688ns 1.244ns 1.569ns 2.739ns } { 0.000ns 0.442ns 0.442ns 0.442ns 0.292ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.385 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.385 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[3] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "11.261 ns" { vga_vl:inst|hcnt[3] vga_vl:inst|LessThan~1901 vga_vl:inst|LessThan~1902 vga_vl:inst|pixel[0]~1279 vga_vl:inst|pixel[0]~1283 VGA_RGB[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.261 ns" { vga_vl:inst|hcnt[3] vga_vl:inst|LessThan~1901 vga_vl:inst|LessThan~1902 vga_vl:inst|pixel[0]~1279 vga_vl:inst|pixel[0]~1283 VGA_RGB[0] } { 0.000ns 1.279ns 0.688ns 1.244ns 1.569ns 2.739ns } { 0.000ns 0.442ns 0.442ns 0.442ns 0.292ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0 0 "All timing requirements were met. See Report window for more details." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 15:43:12 2006 " "Info: Processing ended: Sat Oct 21 15:43:12 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}