colorbar.tan.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "vga_vl:inst\|hsyncint " "Info: Detected ripple clock \"vga_vl:inst\|hsyncint\" as buffer" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 104 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "vga_vl:inst\|hsyncint" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 register vga_vl:inst\|vcnt\[5\] register vga_vl:inst\|enable 2.969 ns " "Info: Slack time is 2.969 ns for clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"vga_vl:inst\|vcnt\[5\]\" and destination register \"vga_vl:inst\|enable\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "52.46 MHz 19.062 ns " "Info: Fmax is 52.46 MHz (period= 19.062 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.074 ns + Largest register register " "Info: + Largest register to register requirement is 7.074 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "12.500 ns + " "Info: + Setup relationship between source and destination is 12.500 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 23.115 ns " "Info: + Latch edge is 23.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 10.615 ns " "Info: - Launch edge is 10.615 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns 10.615 ns inverted 50 " "Info: Clock period of Source clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with inverted offset of 10.615 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.165 ns + Largest " "Info: + Largest clock skew is -5.165 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 destination 2.353 ns + Shortest register " "Info: + Shortest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to destination register is 2.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.711 ns) 2.353 ns vga_vl:inst\|enable 2 REG LC_X21_Y7_N3 5 " "Info: 2: + IC(1.642 ns) + CELL(0.711 ns) = 2.353 ns; Loc. = LC_X21_Y7_N3; Fanout = 5; REG Node = 'vga_vl:inst\|enable'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.22 % ) " "Info: Total cell delay = 0.711 ns ( 30.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns ( 69.78 % ) " "Info: Total interconnect delay = 1.642 ns ( 69.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 7.518 ns - Longest register " "Info: - Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 7.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns vga_vl:inst\|hsyncint 2 REG LC_X21_Y10_N2 13 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X21_Y10_N2; Fanout = 13; REG Node = 'vga_vl:inst\|hsyncint'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.609 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.198 ns) + CELL(0.711 ns) 7.518 ns vga_vl:inst\|vcnt\[5\] 3 REG LC_X22_Y6_N0 5 " "Info: 3: + IC(4.198 ns) + CELL(0.711 ns) = 7.518 ns; Loc. = LC_X22_Y6_N0; Fanout = 5; REG Node = 'vga_vl:inst\|vcnt\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "4.909 ns" { vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 21.89 % ) " "Info: Total cell delay = 1.646 ns ( 21.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.872 ns ( 78.11 % ) " "Info: Total interconnect delay = 5.872 ns ( 78.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.105 ns - Longest register register " "Info: - Longest register to register delay is 4.105 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|vcnt\[5\] 1 REG LC_X22_Y6_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y6_N0; Fanout = 5; REG Node = 'vga_vl:inst\|vcnt\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "" { vga_vl:inst|vcnt[5] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.442 ns) 2.029 ns vga_vl:inst\|always4~150 2 COMB LC_X21_Y7_N9 2 " "Info: 2: + IC(1.587 ns) + CELL(0.442 ns) = 2.029 ns; Loc. = LC_X21_Y7_N9; Fanout = 2; COMB Node = 'vga_vl:inst\|always4~150'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.029 ns" { vga_vl:inst|vcnt[5] vga_vl:inst|always4~150 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.590 ns) 3.067 ns vga_vl:inst\|always4~152 3 COMB LC_X21_Y7_N0 1 " "Info: 3: + IC(0.448 ns) + CELL(0.590 ns) = 3.067 ns; Loc. = LC_X21_Y7_N0; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~152'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "1.038 ns" { vga_vl:inst|always4~150 vga_vl:inst|always4~152 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.363 ns vga_vl:inst\|always4~153 4 COMB LC_X21_Y7_N1 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.363 ns; Loc. = LC_X21_Y7_N1; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~153'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "0.296 ns" { vga_vl:inst|always4~152 vga_vl:inst|always4~153 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.309 ns) 4.105 ns vga_vl:inst\|enable 5 REG LC_X21_Y7_N3 5 " "Info: 5: + IC(0.433 ns) + CELL(0.309 ns) = 4.105 ns; Loc. = LC_X21_Y7_N3; Fanout = 5; REG Node = 'vga_vl:inst\|enable'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "0.742 ns" { vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/src/vga_vl.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.455 ns ( 35.44 % ) " "Info: Total cell delay = 1.455 ns ( 35.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.650 ns ( 64.56 % ) " "Info: Total interconnect delay = 2.650 ns ( 64.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "4.105 ns" { vga_vl:inst|vcnt[5] vga_vl:inst|always4~150 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.105 ns" { vga_vl:inst|vcnt[5] vga_vl:inst|always4~150 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } { 0.000ns 1.587ns 0.448ns 0.182ns 0.433ns } { 0.000ns 0.442ns 0.590ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.353 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.518 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[5] } { 0.000ns 1.674ns 4.198ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ColorBar" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/db/ColorBar.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/vga/Proj/" "" "4.105 ns" { vga_vl:inst|vcnt[5] vga_vl:inst|always4~150 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.105 ns" { vga_vl:inst|vcnt[5] vga_vl:inst|always4~150 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } { 0.000ns 1.587ns 0.448ns 0.182ns 0.433ns } { 0.000ns 0.442ns 0.590ns 0.114ns 0.309ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}