ps2tolcd.map.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "shift_key_on ps2_keyboard.v(211) " "Info (10035): Verilog HDL or VHDL information at ps2_keyboard.v(211): object \"shift_key_on\" declared but not used" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 211 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(416) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(416): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 416 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 ps2_keyboard.v(424) " "Warning (10271): Verilog HDL Case Statement warning at ps2_keyboard.v(424): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 424 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(427) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(427): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 427 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(428) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(428): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 428 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 ps2_keyboard.v(430) " "Warning (10271): Verilog HDL Case Statement warning at ps2_keyboard.v(430): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 430 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(433) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(433): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 433 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(434) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(434): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 434 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2_keyboard.v(436) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(436): truncated value with size 32 to match size of target (1)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 436 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2_keyboard.v(454) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(454): truncated value with size 32 to match size of target (4)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 454 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 ps2_keyboard.v(483) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(483): truncated value with size 32 to match size of target (12)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 483 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ps2_keyboard.v(491) " "Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(491): truncated value with size 32 to match size of target (8)" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 491 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_256 div_256:inst1 " "Info: Elaborating entity \"div_256\" for hierarchy \"div_256:inst1\"" {  } { { "ps2tolcd.bdf" "inst1" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 184 104 200 280 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 div_256.v(16) " "Warning (10230): Verilog HDL assignment warning at div_256.v(16): truncated value with size 32 to match size of target (7)" {  } { { "../SRC/div_256.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ps2_keyboard_interface:inst3\|rx_ascii\[7\] data_in GND " "Warning: Reduced register \"ps2_keyboard_interface:inst3\|rx_ascii\[7\]\" with stuck data_in port to stuck value GND" {  } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 557 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "div16:inst\|count\[0\] div_256:inst1\|count\[0\] " "Info: Duplicate register \"div16:inst\|count\[0\]\" merged to single register \"div_256:inst1\|count\[0\]\"" {  } { { "../SRC/DIV16.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/DIV16.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div16:inst\|count\[1\] div_256:inst1\|count\[1\] " "Info: Duplicate register \"div16:inst\|count\[1\]\" merged to single register \"div_256:inst1\|count\[1\]\"" {  } { { "../SRC/DIV16.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/DIV16.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "div16:inst\|count\[2\] div_256:inst1\|count\[2\] " "Info: Duplicate register \"div16:inst\|count\[2\]\" merged to single register \"div_256:inst1\|count\[2\]\"" {  } { { "../SRC/DIV16.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/DIV16.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "div16:inst\|count\[3\] div_256:inst1\|count\[3\] " "Info: Duplicate register \"div16:inst\|count\[3\]\" merged to single register \"div_256:inst1\|count\[3\]\"" {  } { { "../SRC/DIV16.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/DIV16.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}