ps2tolcd.asm.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 15:40:00 2006 " "Info: Processing started: Sat Oct 21 15:40:00 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ps2tolcd -c ps2tolcd " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ps2tolcd -c ps2tolcd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WPGMIO_CANT_FIT_ASM" "" "Warning: Size of device data exceeds memory capacity of configuration device" {  } {  } 0 0 "Size of device data exceeds memory capacity of configuration device" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 15:40:01 2006 " "Info: Processing ended: Sat Oct 21 15:40:01 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}