📄 ps2tolcd.fit.qmsg
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.917 ns register register " "Info: Estimated most critical path is register to register delay of 10.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst3\|left_shift_key 1 REG LAB_X14_Y11 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y11; Fanout = 15; REG Node = 'ps2_keyboard_interface:inst3\|left_shift_key'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_keyboard_interface:inst3|left_shift_key } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 239 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.590 ns) 1.446 ns ps2_keyboard_interface:inst3\|rx_shift_key_on~0 2 COMB LAB_X15_Y12 45 " "Info: 2: + IC(0.856 ns) + CELL(0.590 ns) = 1.446 ns; Loc. = LAB_X15_Y12; Fanout = 45; COMB Node = 'ps2_keyboard_interface:inst3\|rx_shift_key_on~0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.446 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.114 ns) 2.336 ns rtl~5185 3 COMB LAB_X14_Y12 9 " "Info: 3: + IC(0.776 ns) + CELL(0.114 ns) = 2.336 ns; Loc. = LAB_X14_Y12; Fanout = 9; COMB Node = 'rtl~5185'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.890 ns" { ps2_keyboard_interface:inst3|rx_shift_key_on~0 rtl~5185 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.289 ns) + CELL(0.114 ns) 3.739 ns rtl~77 4 COMB LAB_X13_Y9 2 " "Info: 4: + IC(1.289 ns) + CELL(0.114 ns) = 3.739 ns; Loc. = LAB_X13_Y9; Fanout = 2; COMB Node = 'rtl~77'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.403 ns" { rtl~5185 rtl~77 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.799 ns) + CELL(0.590 ns) 5.128 ns ps2_keyboard_interface:inst3\|reduce_nor~776 5 COMB LAB_X13_Y11 1 " "Info: 5: + IC(0.799 ns) + CELL(0.590 ns) = 5.128 ns; Loc. = LAB_X13_Y11; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~776'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.389 ns" { rtl~77 ps2_keyboard_interface:inst3|reduce_nor~776 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.799 ns) + CELL(0.590 ns) 6.517 ns ps2_keyboard_interface:inst3\|reduce_nor~777 6 COMB LAB_X14_Y9 1 " "Info: 6: + IC(0.799 ns) + CELL(0.590 ns) = 6.517 ns; Loc. = LAB_X14_Y9; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~777'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.389 ns" { ps2_keyboard_interface:inst3|reduce_nor~776 ps2_keyboard_interface:inst3|reduce_nor~777 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.292 ns) 7.887 ns ps2_keyboard_interface:inst3\|reduce_nor~778 7 COMB LAB_X14_Y10 2 " "Info: 7: + IC(1.078 ns) + CELL(0.292 ns) = 7.887 ns; Loc. = LAB_X14_Y10; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~778'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.370 ns" { ps2_keyboard_interface:inst3|reduce_nor~777 ps2_keyboard_interface:inst3|reduce_nor~778 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.590 ns) 8.777 ns ps2_keyboard_interface:inst3\|reduce_nor~797 8 COMB LAB_X15_Y10 2 " "Info: 8: + IC(0.300 ns) + CELL(0.590 ns) = 8.777 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~797'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.890 ns" { ps2_keyboard_interface:inst3|reduce_nor~778 ps2_keyboard_interface:inst3|reduce_nor~797 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 9.441 ns ps2_keyboard_interface:inst3\|reduce_or~1154 9 COMB LAB_X15_Y10 2 " "Info: 9: + IC(0.074 ns) + CELL(0.590 ns) = 9.441 ns; Loc. = LAB_X15_Y10; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1154'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.664 ns" { ps2_keyboard_interface:inst3|reduce_nor~797 ps2_keyboard_interface:inst3|reduce_or~1154 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.114 ns) 10.105 ns ps2_keyboard_interface:inst3\|reduce_or~14 10 COMB LAB_X15_Y10 1 " "Info: 10: + IC(0.550 ns) + CELL(0.114 ns) = 10.105 ns; Loc. = LAB_X15_Y10; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~14'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.664 ns" { ps2_keyboard_interface:inst3|reduce_or~1154 ps2_keyboard_interface:inst3|reduce_or~14 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.738 ns) 10.917 ns ps2_keyboard_interface:inst3\|rx_ascii\[6\] 11 REG LAB_X15_Y10 3 " "Info: 11: + IC(0.074 ns) + CELL(0.738 ns) = 10.917 ns; Loc. = LAB_X15_Y10; Fanout = 3; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[6\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.812 ns" { ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 557 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.322 ns ( 39.59 % ) " "Info: Total cell delay = 4.322 ns ( 39.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.595 ns ( 60.41 % ) " "Info: Total interconnect delay = 6.595 ns ( 60.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "10.917 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 rtl~5185 rtl~77 ps2_keyboard_interface:inst3|reduce_nor~776 ps2_keyboard_interface:inst3|reduce_nor~777 ps2_keyboard_interface:inst3|reduce_nor~778 ps2_keyboard_interface:inst3|reduce_nor~797 ps2_keyboard_interface:inst3|reduce_or~1154 ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 6 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 6%" { } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Warning: Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ps2_clk a permanently disabled " "Info: Pin ps2_clk has a permanently disabled output enable" { } { { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 264 608 784 280 "ps2_clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_clk } "NODE_NAME" } "" } } { "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" "" { ps2_clk } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} } { } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lcd_rw GND " "Info: Pin lcd_rw has GND driving its datain port" { } { { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 560 856 1032 576 "lcd_rw" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd_rw" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { lcd_rw } "NODE_NAME" } "" } } { "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" "" { lcd_rw } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led\[7\] GND " "Info: Pin led\[7\] has GND driving its datain port" { } { { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 360 624 800 376 "led\[7..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "led\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { led[7] } "NODE_NAME" } "" } } { "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" "" { led[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ps2_clk VCC " "Info: Pin ps2_clk has VCC driving its datain port" { } { { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 264 608 784 280 "ps2_clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_clk } "NODE_NAME" } "" } } { "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" "" { ps2_clk } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "ps2_keyboard_interface:inst3\|ps2_data_hi_z~29 (inverted) " "Info: Following pins have the same output enable: ps2_keyboard_interface:inst3\|ps2_data_hi_z~29 (inverted)" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ps2_data LVTTL " "Info: Type bidirectional pin ps2_data uses the LVTTL I/O standard" { } { { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 280 608 784 296 "ps2_data" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ps2_data" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_data } "NODE_NAME" } "" } } { "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.fld" "" "" { ps2_data } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} } { } 0 0 "Following pins have the same output enable: %1!s!" 0 0} } { } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 15:39:59 2006 " "Info: Processing ended: Sat Oct 21 15:39:59 2006" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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