ps2tolcd.fit.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 15:39:54 2006 " "Info: Processing started: Sat Oct 21 15:39:54 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ps2tolcd -c ps2tolcd " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ps2tolcd -c ps2tolcd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ps2tolcd EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"ps2tolcd\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_TOP" "" "Info: Selected Migration Device List" { { "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_SUB" "EP1C12Q240C8 " "Info: Selected EP1C12Q240C8 for migration" {  } {  } 0 0 "Selected %1!s! for migration" 0 0}  } {  } 0 0 "Selected Migration Device List" 0 0}
{ "Info" "IMPP_MPP_NUM_MIGRATABLE_IO" "227 " "Info: Selected migration device list is legal with 227 total of migratable pins" {  } {  } 0 0 "Selected migration device list is legal with %1!d! total of migratable pins" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFYGR_FYGR_MIGRATION_PIN_CANNOT_BE_USED_AS" "12 regular " "Info: Selected device migration path cannot use 12 pins as \"regular\" I/Os" { { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "80 " "Info: Pin \"80\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "81 " "Info: Pin \"81\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "96 " "Info: Pin \"96\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "97 " "Info: Pin \"97\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "102 " "Info: Pin \"102\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "103 " "Info: Pin \"103\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "198 " "Info: Pin \"198\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "199 " "Info: Pin \"199\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "204 " "Info: Pin \"204\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "205 " "Info: Pin \"205\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "220 " "Info: Pin \"220\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "221 " "Info: Pin \"221\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0}  } {  } 2 0 "Selected device migration path cannot use %1!d! pins as \"%2!s!\" I/Os" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "mclk Global clock in PIN 29 " "Info: Automatically promoted signal \"mclk\" to use Global clock in PIN 29" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "div_256:inst1\|clk Global clock " "Info: Automatically promoted signal \"div_256:inst1\|clk\" to use Global clock" {  } { { "../SRC/div_256.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lcd:inst2\|clk_int Global clock " "Info: Automatically promoted some destinations of signal \"lcd:inst2\|clk_int\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:inst2\|clk_int " "Info: Destination \"lcd:inst2\|clk_int\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 79 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 79 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}