ps2tolcd.smp_dump.txt

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

State Machine - |ps2tolcd|ps2_keyboard_interface:inst3|m1_state
Name m1_state.m1_tx_error_no_keyboard_ack m1_state.m1_rx_falling_edge_marker m1_state.m1_rx_rising_edge_marker m1_state.m1_rx_clk_l m1_state.m1_tx_reset_timer m1_state.m1_tx_force_clk_l m1_state.m1_tx_first_wait_clk_h m1_state.m1_tx_first_wait_clk_l m1_state.m1_tx_wait_clk_h m1_state.m1_tx_rising_edge_marker m1_state.m1_tx_clk_h m1_state.m1_tx_clk_l m1_state.m1_tx_wait_keyboard_ack m1_state.m1_tx_done_recovery m1_state.m1_rx_clk_h 
m1_state.m1_rx_clk_h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
m1_state.m1_tx_done_recovery 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
m1_state.m1_tx_wait_keyboard_ack 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
m1_state.m1_tx_clk_l 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
m1_state.m1_tx_clk_h 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
m1_state.m1_tx_rising_edge_marker 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
m1_state.m1_tx_wait_clk_h 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
m1_state.m1_tx_first_wait_clk_l 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
m1_state.m1_tx_first_wait_clk_h 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
m1_state.m1_tx_force_clk_l 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
m1_state.m1_tx_reset_timer 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
m1_state.m1_rx_clk_l 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
m1_state.m1_rx_rising_edge_marker 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
m1_state.m1_rx_falling_edge_marker 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
m1_state.m1_tx_error_no_keyboard_ack 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |ps2tolcd|lcd:inst2|state
Name state.IDLE state.WRITERAM state.SETDDRAM state.SETCGRAM state.SETFUNCTION state.SHIFT state.SWITCHMODE state.SETMODE state.RETURNCURSOR state.CLEAR 
state.IDLE 0 0 0 0 0 0 0 0 0 0 
state.SWITCHMODE 1 0 0 0 0 0 1 0 0 0 
state.RETURNCURSOR 1 0 0 0 0 0 0 0 1 0 
state.WRITERAM 1 1 0 0 0 0 0 0 0 0 
state.SETDDRAM 1 0 1 0 0 0 0 0 0 0 
state.CLEAR 1 0 0 0 0 0 0 0 0 1 
state.SETMODE 1 0 0 0 0 0 0 1 0 0 
state.SHIFT 1 0 0 0 0 1 0 0 0 0 
state.SETFUNCTION 1 0 0 0 1 0 0 0 0 0 
state.SETCGRAM 1 0 0 1 0 0 0 0 0 0