ps2tolcd.hier_info

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

|ps2tolcd
lcd_e <= lcd:inst2.lcd_e
mclk => div16:inst.clk
mclk => div_256:inst1.mclk
reset => div16:inst.rst
reset => lcd:inst2.rst
reset => div_256:inst1.reset
reset => ps2_keyboard_interface:inst3.reset
ps2_clk <= ps2_keyboard_interface:inst3.ps2_clk
ps2_data <= ps2_keyboard_interface:inst3.ps2_data
lcd_rw <= lcd:inst2.lcd_rw
lcd_rs <= lcd:inst2.lcd_rs
data[0] <= lcd:inst2.data[0]
data[1] <= lcd:inst2.data[1]
data[2] <= lcd:inst2.data[2]
data[3] <= lcd:inst2.data[3]
data[4] <= lcd:inst2.data[4]
data[5] <= lcd:inst2.data[5]
data[6] <= lcd:inst2.data[6]
data[7] <= lcd:inst2.data[7]
led[0] <= ps2_keyboard_interface:inst3.rx_ascii[0]
led[1] <= ps2_keyboard_interface:inst3.rx_ascii[1]
led[2] <= ps2_keyboard_interface:inst3.rx_ascii[2]
led[3] <= ps2_keyboard_interface:inst3.rx_ascii[3]
led[4] <= ps2_keyboard_interface:inst3.rx_ascii[4]
led[5] <= ps2_keyboard_interface:inst3.rx_ascii[5]
led[6] <= ps2_keyboard_interface:inst3.rx_ascii[6]
led[7] <= ps2_keyboard_interface:inst3.rx_ascii[7]


|ps2tolcd|lcd:inst2
clk => clkcnt[14].CLK
clk => clkcnt[13].CLK
clk => clkcnt[12].CLK
clk => clkcnt[11].CLK
clk => clkcnt[10].CLK
clk => clkcnt[9].CLK
clk => clkcnt[8].CLK
clk => clkcnt[7].CLK
clk => clkcnt[6].CLK
clk => clkcnt[5].CLK
clk => clkcnt[4].CLK
clk => clkcnt[3].CLK
clk => clkcnt[2].CLK
clk => clkcnt[1].CLK
clk => clkcnt[0].CLK
clk => clkcnt[15].CLK
rst => clkdiv~0.OUTPUTSELECT
rst => clk_int~0.OUTPUTSELECT
rst => lcd_e~0.OUTPUTSELECT
rst => flag.ACLR
rst => data_in_buf[7].LATCH_ENABLE
rst => clkcnt~23.OUTPUTSELECT
rst => clkcnt~22.OUTPUTSELECT
rst => clkcnt~21.OUTPUTSELECT
rst => clkcnt~20.OUTPUTSELECT
rst => clkcnt~19.OUTPUTSELECT
rst => clkcnt~18.OUTPUTSELECT
rst => clkcnt~17.OUTPUTSELECT
rst => clkcnt~16.OUTPUTSELECT
rst => data_in_buf[6].LATCH_ENABLE
rst => data_in_buf[5].LATCH_ENABLE
rst => data_in_buf[4].LATCH_ENABLE
rst => data_in_buf[3].LATCH_ENABLE
rst => data_in_buf[2].LATCH_ENABLE
rst => data_in_buf[1].LATCH_ENABLE
rst => data_in_buf[0].LATCH_ENABLE
rst => clkcnt~24.OUTPUTSELECT
rst => clkcnt~25.OUTPUTSELECT
rst => clkcnt~26.OUTPUTSELECT
rst => clkcnt~27.OUTPUTSELECT
rst => clkcnt~28.OUTPUTSELECT
rst => clkcnt~29.OUTPUTSELECT
rst => clkcnt~30.OUTPUTSELECT
rst => clkcnt~31.OUTPUTSELECT
rst => lcd_rs~reg0.ENA
rst => lcd_rw~reg0.ENA
rst => data[7]~reg0.ENA
rst => data[6]~reg0.ENA
rst => data[5]~reg0.ENA
rst => data[4]~reg0.ENA
rst => data[3]~reg0.ENA
rst => data[2]~reg0.ENA
rst => data[1]~reg0.ENA
rst => data[0]~reg0.ENA
rst => state~9.IN1
data_in[0] => data_in_buf[0].DATAIN
data_in[1] => data_in_buf[1].DATAIN
data_in[2] => data_in_buf[2].DATAIN
data_in[3] => data_in_buf[3].DATAIN
data_in[4] => data_in_buf[4].DATAIN
data_in[5] => data_in_buf[5].DATAIN
data_in[6] => data_in_buf[6].DATAIN
data_in[7] => data_in_buf[7].DATAIN
lcd_e <= lcd_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rw <= lcd_rw~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rs <= lcd_rs~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ps2tolcd|div16:inst
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => count[3].CLK
rst => count[2].ACLR
rst => count[1].ACLR
rst => count[0].ACLR
rst => count[3].ACLR
clk_16 <= count[3].DB_MAX_OUTPUT_PORT_TYPE


|ps2tolcd|ps2_keyboard_interface:inst3
clk => ps2_data_s.CLK
clk => m2_state.CLK
clk => bit_count[3].CLK
clk => bit_count[2].CLK
clk => bit_count[1].CLK
clk => bit_count[0].CLK
clk => q[10].CLK
clk => q[9].CLK
clk => q[8].CLK
clk => q[7].CLK
clk => q[6].CLK
clk => q[5].CLK
clk => q[4].CLK
clk => q[3].CLK
clk => q[2].CLK
clk => q[1].CLK
clk => q[0].CLK
clk => timer_60usec_count[11].CLK
clk => timer_60usec_count[10].CLK
clk => timer_60usec_count[9].CLK
clk => timer_60usec_count[8].CLK
clk => timer_60usec_count[7].CLK
clk => timer_60usec_count[6].CLK
clk => timer_60usec_count[5].CLK
clk => timer_60usec_count[4].CLK
clk => timer_60usec_count[3].CLK
clk => timer_60usec_count[2].CLK
clk => timer_60usec_count[1].CLK
clk => timer_60usec_count[0].CLK
clk => timer_5usec_count[7].CLK
clk => timer_5usec_count[6].CLK
clk => timer_5usec_count[5].CLK
clk => timer_5usec_count[4].CLK
clk => timer_5usec_count[3].CLK
clk => timer_5usec_count[2].CLK
clk => timer_5usec_count[1].CLK
clk => timer_5usec_count[0].CLK
clk => hold_extended.CLK
clk => hold_released.CLK
clk => left_shift_key.CLK
clk => right_shift_key.CLK
clk => rx_extended~reg0.CLK
clk => rx_released~reg0.CLK
clk => rx_scan_code[7]~reg0.CLK
clk => rx_scan_code[6]~reg0.CLK
clk => rx_scan_code[5]~reg0.CLK
clk => rx_scan_code[4]~reg0.CLK
clk => rx_scan_code[3]~reg0.CLK
clk => rx_scan_code[2]~reg0.CLK
clk => rx_scan_code[1]~reg0.CLK
clk => rx_scan_code[0]~reg0.CLK
clk => rx_ascii[7]~reg0.CLK
clk => rx_ascii[6]~reg0.CLK
clk => rx_ascii[5]~reg0.CLK
clk => rx_ascii[4]~reg0.CLK
clk => rx_ascii[3]~reg0.CLK
clk => rx_ascii[2]~reg0.CLK
clk => rx_ascii[1]~reg0.CLK
clk => rx_ascii[0]~reg0.CLK
clk => ps2_clk_s.CLK
clk => m1_state~15.IN1
reset => m2_state~0.OUTPUTSELECT
reset => left_shift_key~2.OUTPUTSELECT
reset => right_shift_key~2.OUTPUTSELECT
reset => rx_extended~1.OUTPUTSELECT
reset => rx_released~1.OUTPUTSELECT
reset => rx_scan_code~8.OUTPUTSELECT
reset => rx_scan_code~9.OUTPUTSELECT
reset => rx_scan_code~10.OUTPUTSELECT
reset => rx_scan_code~11.OUTPUTSELECT
reset => rx_scan_code~12.OUTPUTSELECT
reset => rx_scan_code~13.OUTPUTSELECT
reset => rx_scan_code~14.OUTPUTSELECT
reset => rx_scan_code~15.OUTPUTSELECT
reset => rx_ascii~8.OUTPUTSELECT
reset => rx_ascii~9.OUTPUTSELECT
reset => rx_ascii~10.OUTPUTSELECT
reset => rx_ascii~11.OUTPUTSELECT
reset => rx_ascii~12.OUTPUTSELECT
reset => rx_ascii~13.OUTPUTSELECT
reset => rx_ascii~14.OUTPUTSELECT
reset => rx_ascii~15.OUTPUTSELECT
reset => m1_state~0.OUTPUTSELECT
reset => m1_state~1.OUTPUTSELECT
reset => m1_state~2.OUTPUTSELECT
reset => m1_state~3.OUTPUTSELECT
reset => m1_state~4.OUTPUTSELECT
reset => m1_state~5.OUTPUTSELECT
reset => m1_state~6.OUTPUTSELECT
reset => m1_state~7.OUTPUTSELECT
reset => m1_state~8.OUTPUTSELECT
reset => m1_state~9.OUTPUTSELECT
reset => m1_state~10.OUTPUTSELECT
reset => m1_state~11.OUTPUTSELECT
reset => m1_state~12.OUTPUTSELECT
reset => m1_state~13.OUTPUTSELECT
reset => m1_state~14.OUTPUTSELECT
reset => always5~0.IN0
reset => q~22.OUTPUTSELECT
reset => q~23.OUTPUTSELECT
reset => q~24.OUTPUTSELECT
reset => q~25.OUTPUTSELECT
reset => q~26.OUTPUTSELECT
reset => q~27.OUTPUTSELECT
reset => q~28.OUTPUTSELECT
reset => q~29.OUTPUTSELECT
reset => q~30.OUTPUTSELECT
reset => q~31.OUTPUTSELECT
reset => q~32.OUTPUTSELECT
reset => always9~0.IN0
ps2_clk <= ps2_clk~0
ps2_data <= ps2_data~0
rx_extended <= rx_extended~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_released <= rx_released~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_shift_key_on <= rx_shift_key_on~0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[0] <= rx_scan_code[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[1] <= rx_scan_code[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[2] <= rx_scan_code[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[3] <= rx_scan_code[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[4] <= rx_scan_code[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[5] <= rx_scan_code[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[6] <= rx_scan_code[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[7] <= rx_scan_code[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[0] <= rx_ascii[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[1] <= rx_ascii[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[2] <= rx_ascii[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[3] <= rx_ascii[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[4] <= rx_ascii[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[5] <= rx_ascii[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[6] <= rx_ascii[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[7] <= rx_ascii[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_ready <= Decoder~0.DB_MAX_OUTPUT_PORT_TYPE
rx_read => m2_next_state.DATAB
tx_data[0] => tx_parity_bit.IN7
tx_data[0] => q~20.DATAB
tx_data[1] => tx_parity_bit.IN6
tx_data[1] => q~19.DATAB
tx_data[2] => tx_parity_bit.IN5
tx_data[2] => q~18.DATAB
tx_data[3] => tx_parity_bit.IN4
tx_data[3] => q~17.DATAB
tx_data[4] => tx_parity_bit.IN3
tx_data[4] => q~16.DATAB
tx_data[5] => tx_parity_bit.IN2
tx_data[5] => q~15.DATAB
tx_data[6] => tx_parity_bit.IN1
tx_data[6] => q~14.DATAB
tx_data[7] => tx_parity_bit.IN0
tx_data[7] => q~13.DATAB
tx_write => m1_next_state~0.OUTPUTSELECT
tx_write => m1_next_state~1.OUTPUTSELECT
tx_write => m1_next_state.m1_tx_reset_timer.IN2
tx_write => tx_write_ack_o~0.IN1
tx_write => tx_write_ack_o~1.IN1
tx_write_ack_o <= tx_write_ack_o~2.DB_MAX_OUTPUT_PORT_TYPE
tx_error_no_keyboard_ack <= m1_state.m1_tx_error_no_keyboard_ack.DB_MAX_OUTPUT_PORT_TYPE


|ps2tolcd|div_256:inst1
mclk => count[5].CLK
mclk => count[4].CLK
mclk => count[3].CLK
mclk => count[2].CLK
mclk => count[1].CLK
mclk => count[0].CLK
mclk => clk~reg0.CLK
mclk => count[6].CLK
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => count[6].ACLR
reset => clk~reg0.ENA
clk <= clk~reg0.DB_MAX_OUTPUT_PORT_TYPE