📄 ps2tolcd.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "24 " "Warning: Found 24 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[15\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[15\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[12\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[12\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[14\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[14\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[13\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[13\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[11\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[11\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[10\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[10\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[9\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[9\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[8\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[8\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[6\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[6\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[7\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[7\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[5\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[4\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[3\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[2\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~5174 " "Info: Detected gated clock \"rtl~5174\" as buffer" { } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~5174" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~5175 " "Info: Detected gated clock \"rtl~5175\" as buffer" { } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~5175" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~5173 " "Info: Detected gated clock \"rtl~5173\" as buffer" { } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~5173" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~5172 " "Info: Detected gated clock \"rtl~5172\" as buffer" { } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~5172" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[1\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_256:inst1\|count\[3\] " "Info: Detected ripple clock \"div_256:inst1\|count\[3\]\" as buffer" { } { { "../SRC/div_256.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 12 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div_256:inst1\|count\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst2\|clkcnt\[0\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkcnt\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_256:inst1\|clk " "Info: Detected ripple clock \"div_256:inst1\|clk\" as buffer" { } { { "../SRC/div_256.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div_256:inst1\|clk" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clk_int " "Info: Detected ripple clock \"lcd:inst2\|clk_int\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 79 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clk_int" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst2\|clkdiv " "Info: Detected ripple clock \"lcd:inst2\|clkdiv\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 72 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst2\|clkdiv" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mclk register ps2_keyboard_interface:inst3\|left_shift_key register ps2_keyboard_interface:inst3\|rx_ascii\[6\] 72.31 MHz 13.829 ns Internal " "Info: Clock \"mclk\" has Internal fmax of 72.31 MHz between source register \"ps2_keyboard_interface:inst3\|left_shift_key\" and destination register \"ps2_keyboard_interface:inst3\|rx_ascii\[6\]\" (period= 13.829 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.568 ns + Longest register register " "Info: + Longest register to register delay is 13.568 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst3\|left_shift_key 1 REG LC_X14_Y11_N1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N1; Fanout = 15; REG Node = 'ps2_keyboard_interface:inst3\|left_shift_key'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_keyboard_interface:inst3|left_shift_key } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 239 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.346 ns) + CELL(0.590 ns) 1.936 ns ps2_keyboard_interface:inst3\|rx_shift_key_on~0 2 COMB LC_X15_Y12_N6 45 " "Info: 2: + IC(1.346 ns) + CELL(0.590 ns) = 1.936 ns; Loc. = LC_X15_Y12_N6; Fanout = 45; COMB Node = 'ps2_keyboard_interface:inst3\|rx_shift_key_on~0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.936 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.292 ns) 3.439 ns rtl~5185 3 COMB LC_X14_Y12_N8 9 " "Info: 3: + IC(1.211 ns) + CELL(0.292 ns) = 3.439 ns; Loc. = LC_X14_Y12_N8; Fanout = 9; COMB Node = 'rtl~5185'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.503 ns" { ps2_keyboard_interface:inst3|rx_shift_key_on~0 rtl~5185 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.063 ns) + CELL(0.292 ns) 5.794 ns rtl~4 4 COMB LC_X19_Y11_N7 2 " "Info: 4: + IC(2.063 ns) + CELL(0.292 ns) = 5.794 ns; Loc. = LC_X19_Y11_N7; Fanout = 2; COMB Node = 'rtl~4'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.355 ns" { rtl~5185 rtl~4 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.664 ns) + CELL(0.114 ns) 7.572 ns ps2_keyboard_interface:inst3\|reduce_or~1140 5 COMB LC_X16_Y10_N4 1 " "Info: 5: + IC(1.664 ns) + CELL(0.114 ns) = 7.572 ns; Loc. = LC_X16_Y10_N4; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1140'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.778 ns" { rtl~4 ps2_keyboard_interface:inst3|reduce_or~1140 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.292 ns) 8.308 ns ps2_keyboard_interface:inst3\|reduce_or~1142 6 COMB LC_X16_Y10_N6 2 " "Info: 6: + IC(0.444 ns) + CELL(0.292 ns) = 8.308 ns; Loc. = LC_X16_Y10_N6; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1142'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.736 ns" { ps2_keyboard_interface:inst3|reduce_or~1140 ps2_keyboard_interface:inst3|reduce_or~1142 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.424 ns) + CELL(0.590 ns) 9.322 ns ps2_keyboard_interface:inst3\|reduce_or~1146 7 COMB LC_X16_Y10_N9 2 " "Info: 7: + IC(0.424 ns) + CELL(0.590 ns) = 9.322 ns; Loc. = LC_X16_Y10_N9; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1146'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.014 ns" { ps2_keyboard_interface:inst3|reduce_or~1142 ps2_keyboard_interface:inst3|reduce_or~1146 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.771 ns) + CELL(0.114 ns) 10.207 ns ps2_keyboard_interface:inst3\|reduce_nor~785 8 COMB LC_X15_Y10_N1 2 " "Info: 8: + IC(0.771 ns) + CELL(0.114 ns) = 10.207 ns; Loc. = LC_X15_Y10_N1; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~785'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.885 ns" { ps2_keyboard_interface:inst3|reduce_or~1146 ps2_keyboard_interface:inst3|reduce_nor~785 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.590 ns) 11.243 ns ps2_keyboard_interface:inst3\|reduce_nor~797 9 COMB LC_X15_Y10_N0 2 " "Info: 9: + IC(0.446 ns) + CELL(0.590 ns) = 11.243 ns; Loc. = LC_X15_Y10_N0; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_nor~797'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.036 ns" { ps2_keyboard_interface:inst3|reduce_nor~785 ps2_keyboard_interface:inst3|reduce_nor~797 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.114 ns) 11.799 ns ps2_keyboard_interface:inst3\|reduce_or~1154 10 COMB LC_X15_Y10_N7 2 " "Info: 10: + IC(0.442 ns) + CELL(0.114 ns) = 11.799 ns; Loc. = LC_X15_Y10_N7; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~1154'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.556 ns" { ps2_keyboard_interface:inst3|reduce_nor~797 ps2_keyboard_interface:inst3|reduce_or~1154 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.590 ns) 12.826 ns ps2_keyboard_interface:inst3\|reduce_or~14 11 COMB LC_X15_Y10_N3 1 " "Info: 11: + IC(0.437 ns) + CELL(0.590 ns) = 12.826 ns; Loc. = LC_X15_Y10_N3; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst3\|reduce_or~14'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.027 ns" { ps2_keyboard_interface:inst3|reduce_or~1154 ps2_keyboard_interface:inst3|reduce_or~14 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.309 ns) 13.568 ns ps2_keyboard_interface:inst3\|rx_ascii\[6\] 12 REG LC_X15_Y10_N8 3 " "Info: 12: + IC(0.433 ns) + CELL(0.309 ns) = 13.568 ns; Loc. = LC_X15_Y10_N8; Fanout = 3; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[6\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.742 ns" { ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 557 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.887 ns ( 28.65 % ) " "Info: Total cell delay = 3.887 ns ( 28.65 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.681 ns ( 71.35 % ) " "Info: Total interconnect delay = 9.681 ns ( 71.35 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "13.568 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 rtl~5185 rtl~4 ps2_keyboard_interface:inst3|reduce_or~1140 ps2_keyboard_interface:inst3|reduce_or~1142 ps2_keyboard_interface:inst3|reduce_or~1146 ps2_keyboard_interface:inst3|reduce_nor~785 ps2_keyboard_interface:inst3|reduce_nor~797 ps2_keyboard_interface:inst3|reduce_or~1154 ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.568 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 rtl~5185 rtl~4 ps2_keyboard_interface:inst3|reduce_or~1140 ps2_keyboard_interface:inst3|reduce_or~1142 ps2_keyboard_interface:inst3|reduce_or~1146 ps2_keyboard_interface:inst3|reduce_nor~785 ps2_keyboard_interface:inst3|reduce_nor~797 ps2_keyboard_interface:inst3|reduce_or~1154 ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } { 0.000ns 1.346ns 1.211ns 2.063ns 1.664ns 0.444ns 0.424ns 0.771ns 0.446ns 0.442ns 0.437ns 0.433ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.114ns 0.292ns 0.590ns 0.114ns 0.590ns 0.114ns 0.590ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 7.711 ns + Shortest register " "Info: + Shortest clock path from clock \"mclk\" to destination register is 7.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns div_256:inst1\|clk 2 REG LC_X27_Y10_N7 58 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.697 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.834 ns) + CELL(0.711 ns) 7.711 ns ps2_keyboard_interface:inst3\|rx_ascii\[6\] 3 REG LC_X15_Y10_N8 3 " "Info: 3: + IC(3.834 ns) + CELL(0.711 ns) = 7.711 ns; Loc. = LC_X15_Y10_N8; Fanout = 3; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[6\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.545 ns" { div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 557 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.40 % ) " "Info: Total cell delay = 3.115 ns ( 40.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.596 ns ( 59.60 % ) " "Info: Total interconnect delay = 4.596 ns ( 59.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.711 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.711 ns" { mclk mclk~out0 div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[6] } { 0.000ns 0.000ns 0.762ns 3.834ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 7.711 ns - Longest register " "Info: - Longest clock path from clock \"mclk\" to source register is 7.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns div_256:inst1\|clk 2 REG LC_X27_Y10_N7 58 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.697 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.834 ns) + CELL(0.711 ns) 7.711 ns ps2_keyboard_interface:inst3\|left_shift_key 3 REG LC_X14_Y11_N1 15 " "Info: 3: + IC(3.834 ns) + CELL(0.711 ns) = 7.711 ns; Loc. = LC_X14_Y11_N1; Fanout = 15; REG Node = 'ps2_keyboard_interface:inst3\|left_shift_key'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.545 ns" { div_256:inst1|clk ps2_keyboard_interface:inst3|left_shift_key } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 239 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.40 % ) " "Info: Total cell delay = 3.115 ns ( 40.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.596 ns ( 59.60 % ) " "Info: Total interconnect delay = 4.596 ns ( 59.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.711 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|left_shift_key } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.711 ns" { mclk mclk~out0 div_256:inst1|clk ps2_keyboard_interface:inst3|left_shift_key } { 0.000ns 0.000ns 0.762ns 3.834ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.711 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.711 ns" { mclk mclk~out0 div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[6] } { 0.000ns 0.000ns 0.762ns 3.834ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.711 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|left_shift_key } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.711 ns" { mclk mclk~out0 div_256:inst1|clk ps2_keyboard_interface:inst3|left_shift_key } { 0.000ns 0.000ns 0.762ns 3.834ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 239 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 557 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "13.568 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 rtl~5185 rtl~4 ps2_keyboard_interface:inst3|reduce_or~1140 ps2_keyboard_interface:inst3|reduce_or~1142 ps2_keyboard_interface:inst3|reduce_or~1146 ps2_keyboard_interface:inst3|reduce_nor~785 ps2_keyboard_interface:inst3|reduce_nor~797 ps2_keyboard_interface:inst3|reduce_or~1154 ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.568 ns" { ps2_keyboard_interface:inst3|left_shift_key ps2_keyboard_interface:inst3|rx_shift_key_on~0 rtl~5185 rtl~4 ps2_keyboard_interface:inst3|reduce_or~1140 ps2_keyboard_interface:inst3|reduce_or~1142 ps2_keyboard_interface:inst3|reduce_or~1146 ps2_keyboard_interface:inst3|reduce_nor~785 ps2_keyboard_interface:inst3|reduce_nor~797 ps2_keyboard_interface:inst3|reduce_or~1154 ps2_keyboard_interface:inst3|reduce_or~14 ps2_keyboard_interface:inst3|rx_ascii[6] } { 0.000ns 1.346ns 1.211ns 2.063ns 1.664ns 0.444ns 0.424ns 0.771ns 0.446ns 0.442ns 0.437ns 0.433ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.114ns 0.292ns 0.590ns 0.114ns 0.590ns 0.114ns 0.590ns 0.309ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.711 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.711 ns" { mclk mclk~out0 div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[6] } { 0.000ns 0.000ns 0.762ns 3.834ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.711 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|left_shift_key } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.711 ns" { mclk mclk~out0 div_256:inst1|clk ps2_keyboard_interface:inst3|left_shift_key } { 0.000ns 0.000ns 0.762ns 3.834ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "mclk 135 " "Warning: Circuit may not operate. Detected 135 non-operational path(s) clocked by clock \"mclk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ps2_keyboard_interface:inst3\|rx_ascii\[4\] lcd:inst2\|data\[4\] mclk 10.815 ns " "Info: Found hold time violation between source pin or register \"ps2_keyboard_interface:inst3\|rx_ascii\[4\]\" and destination pin or register \"lcd:inst2\|data\[4\]\" for clock \"mclk\" (Hold time is 10.815 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "15.143 ns + Largest " "Info: + Largest clock skew is 15.143 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 22.834 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to destination register is 22.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns div_256:inst1\|count\[3\] 2 REG LC_X27_Y11_N2 18 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y11_N2; Fanout = 18; REG Node = 'div_256:inst1\|count\[3\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.697 ns" { mclk div_256:inst1|count[3] } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.075 ns) + CELL(0.935 ns) 8.176 ns lcd:inst2\|clkcnt\[14\] 3 REG LC_X21_Y17_N6 4 " "Info: 3: + IC(4.075 ns) + CELL(0.935 ns) = 8.176 ns; Loc. = LC_X21_Y17_N6; Fanout = 4; REG Node = 'lcd:inst2\|clkcnt\[14\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "5.010 ns" { div_256:inst1|count[3] lcd:inst2|clkcnt[14] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.661 ns) + CELL(0.590 ns) 10.427 ns rtl~5175 4 COMB LC_X20_Y18_N7 1 " "Info: 4: + IC(1.661 ns) + CELL(0.590 ns) = 10.427 ns; Loc. = LC_X20_Y18_N7; Fanout = 1; COMB Node = 'rtl~5175'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.251 ns" { lcd:inst2|clkcnt[14] rtl~5175 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.292 ns) 11.160 ns rtl~5176 5 COMB LC_X20_Y18_N5 2 " "Info: 5: + IC(0.441 ns) + CELL(0.292 ns) = 11.160 ns; Loc. = LC_X20_Y18_N5; Fanout = 2; COMB Node = 'rtl~5176'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.733 ns" { rtl~5175 rtl~5176 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.935 ns) 12.573 ns lcd:inst2\|clkdiv 6 REG LC_X20_Y18_N9 3 " "Info: 6: + IC(0.478 ns) + CELL(0.935 ns) = 12.573 ns; Loc. = LC_X20_Y18_N9; Fanout = 3; REG Node = 'lcd:inst2\|clkdiv'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.413 ns" { rtl~5176 lcd:inst2|clkdiv } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.088 ns) + CELL(0.935 ns) 18.596 ns lcd:inst2\|clk_int 7 REG LC_X8_Y10_N2 26 " "Info: 7: + IC(5.088 ns) + CELL(0.935 ns) = 18.596 ns; Loc. = LC_X8_Y10_N2; Fanout = 26; REG Node = 'lcd:inst2\|clk_int'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "6.023 ns" { lcd:inst2|clkdiv lcd:inst2|clk_int } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.527 ns) + CELL(0.711 ns) 22.834 ns lcd:inst2\|data\[4\] 8 REG LC_X22_Y10_N0 3 " "Info: 8: + IC(3.527 ns) + CELL(0.711 ns) = 22.834 ns; Loc. = LC_X22_Y10_N0; Fanout = 3; REG Node = 'lcd:inst2\|data\[4\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.238 ns" { lcd:inst2|clk_int lcd:inst2|data[4] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.802 ns ( 29.79 % ) " "Info: Total cell delay = 6.802 ns ( 29.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.032 ns ( 70.21 % ) " "Info: Total interconnect delay = 16.032 ns ( 70.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "22.834 ns" { mclk div_256:inst1|count[3] lcd:inst2|clkcnt[14] rtl~5175 rtl~5176 lcd:inst2|clkdiv lcd:inst2|clk_int lcd:inst2|data[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "22.834 ns" { mclk mclk~out0 div_256:inst1|count[3] lcd:inst2|clkcnt[14] rtl~5175 rtl~5176 lcd:inst2|clkdiv lcd:inst2|clk_int lcd:inst2|data[4] } { 0.000ns 0.000ns 0.762ns 4.075ns 1.661ns 0.441ns 0.478ns 5.088ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.292ns 0.935ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 7.691 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to source register is 7.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2tolcd.bdf" "" { Schematic "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/ps2tolcd.bdf" { { 208 -176 -8 224 "mclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns div_256:inst1\|clk 2 REG LC_X27_Y10_N7 58 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N7; Fanout = 58; REG Node = 'div_256:inst1\|clk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.697 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "../SRC/div_256.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/div_256.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.814 ns) + CELL(0.711 ns) 7.691 ns ps2_keyboard_interface:inst3\|rx_ascii\[4\] 3 REG LC_X15_Y8_N9 3 " "Info: 3: + IC(3.814 ns) + CELL(0.711 ns) = 7.691 ns; Loc. = LC_X15_Y8_N9; Fanout = 3; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[4\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "4.525 ns" { div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[4] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 557 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.50 % ) " "Info: Total cell delay = 3.115 ns ( 40.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.576 ns ( 59.50 % ) " "Info: Total interconnect delay = 4.576 ns ( 59.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.691 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.691 ns" { mclk mclk~out0 div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[4] } { 0.000ns 0.000ns 0.762ns 3.814ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "22.834 ns" { mclk div_256:inst1|count[3] lcd:inst2|clkcnt[14] rtl~5175 rtl~5176 lcd:inst2|clkdiv lcd:inst2|clk_int lcd:inst2|data[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "22.834 ns" { mclk mclk~out0 div_256:inst1|count[3] lcd:inst2|clkcnt[14] rtl~5175 rtl~5176 lcd:inst2|clkdiv lcd:inst2|clk_int lcd:inst2|data[4] } { 0.000ns 0.000ns 0.762ns 4.075ns 1.661ns 0.441ns 0.478ns 5.088ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.292ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "7.691 ns" { mclk div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.691 ns" { mclk mclk~out0 div_256:inst1|clk ps2_keyboard_interface:inst3|rx_ascii[4] } { 0.000ns 0.000ns 0.762ns 3.814ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 557 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.119 ns - Shortest register register " "Info: - Shortest register to register delay is 4.119 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst3\|rx_ascii\[4\] 1 REG LC_X15_Y8_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y8_N9; Fanout = 3; REG Node = 'ps2_keyboard_interface:inst3\|rx_ascii\[4\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { ps2_keyboard_interface:inst3|rx_ascii[4] } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/ps2_keyboard.v" 557 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns lcd:inst2\|data_in_buf\[4\] 2 COMB LOOP LC_X15_Y8_N5 3 " "Info: 2: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = LC_X15_Y8_N5; Fanout = 3; COMB LOOP Node = 'lcd:inst2\|data_in_buf\[4\]'" { { "Info" "ITDB_PART_OF_SCC" "lcd:inst2\|data_in_buf\[4\] LC_X15_Y8_N5 " "Info: Loc. = LC_X15_Y8_N5; Node \"lcd:inst2\|data_in_buf\[4\]\"" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { lcd:inst2|data_in_buf[4] } "NODE_NAME" } "" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "" { lcd:inst2|data_in_buf[4] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "0.840 ns" { ps2_keyboard_interface:inst3|rx_ascii[4] lcd:inst2|data_in_buf[4] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.977 ns) + CELL(0.114 ns) 2.931 ns lcd:inst2\|Select~1408 3 COMB LC_X22_Y10_N2 1 " "Info: 3: + IC(1.977 ns) + CELL(0.114 ns) = 2.931 ns; Loc. = LC_X22_Y10_N2; Fanout = 1; COMB Node = 'lcd:inst2\|Select~1408'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "2.091 ns" { lcd:inst2|data_in_buf[4] lcd:inst2|Select~1408 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.738 ns) 4.119 ns lcd:inst2\|data\[4\] 4 REG LC_X22_Y10_N0 3 " "Info: 4: + IC(0.450 ns) + CELL(0.738 ns) = 4.119 ns; Loc. = LC_X22_Y10_N0; Fanout = 3; REG Node = 'lcd:inst2\|data\[4\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ps2tolcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/PROJ/" "" "1.188 ns" { lcd:inst2|Select~1408 lcd:inst2|data[4] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.692 ns ( 41.08 % ) " "Info: Total cell delay = 1.692 ns ( 41.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.427 ns ( 58.92 % ) " "Info: Total interconnect delay = 2.427 ns ( 58.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report⌨️ 快捷键说明
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