ps2tolcd.tan.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 15:40:02 2006 " "Info: Processing started: Sat Oct 21 15:40:02 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off ps2tolcd -c ps2tolcd --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ps2tolcd -c ps2tolcd --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "lcd:inst2\|data_in_buf\[2\] " "Warning: Node \"lcd:inst2\|data_in_buf\[2\]\" is a latch" {  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "lcd:inst2\|data_in_buf\[1\] " "Warning: Node \"lcd:inst2\|data_in_buf\[1\]\" is a latch" {  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "lcd:inst2\|data_in_buf\[0\] " "Warning: Node \"lcd:inst2\|data_in_buf\[0\]\" is a latch" {  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "lcd:inst2\|data_in_buf\[3\] " "Warning: Node \"lcd:inst2\|data_in_buf\[3\]\" is a latch" {  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "lcd:inst2\|data_in_buf\[4\] " "Warning: Node \"lcd:inst2\|data_in_buf\[4\]\" is a latch" {  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "lcd:inst2\|data_in_buf\[6\] " "Warning: Node \"lcd:inst2\|data_in_buf\[6\]\" is a latch" {  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "lcd:inst2\|data_in_buf\[5\] " "Warning: Node \"lcd:inst2\|data_in_buf\[5\]\" is a latch" {  } { { "../SRC/lcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/PS2/SRC/lcd.v" 94 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis found one or more latches implemented as combinational loops" 0 0}