key1.map.qmsg

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "key1.v(89) " "Warning (10270): Verilog HDL statement warning at key1.v(89): incomplete Case Statement has no default case item" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 89 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|key1\|scan_key 16 " "Info: State machine \"\|key1\|scan_key\" contains 16 states" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|key1\|scan_key " "Info: Selected Auto state machine encoding method for state machine \"\|key1\|scan_key\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|key1\|scan_key " "Info: Encoding result for state machine \"\|key1\|scan_key\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "16 " "Info: Completed encoding using 16 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.1111 " "Info: Encoded state bit \"scan_key.1111\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.0001 " "Info: Encoded state bit \"scan_key.0001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.0010 " "Info: Encoded state bit \"scan_key.0010\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.0011 " "Info: Encoded state bit \"scan_key.0011\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.0100 " "Info: Encoded state bit \"scan_key.0100\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.0101 " "Info: Encoded state bit \"scan_key.0101\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.0110 " "Info: Encoded state bit \"scan_key.0110\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.0111 " "Info: Encoded state bit \"scan_key.0111\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.1000 " "Info: Encoded state bit \"scan_key.1000\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.1001 " "Info: Encoded state bit \"scan_key.1001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.1010 " "Info: Encoded state bit \"scan_key.1010\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.1011 " "Info: Encoded state bit \"scan_key.1011\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.1100 " "Info: Encoded state bit \"scan_key.1100\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.1101 " "Info: Encoded state bit \"scan_key.1101\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.1110 " "Info: Encoded state bit \"scan_key.1110\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "scan_key.0000 " "Info: Encoded state bit \"scan_key.0000\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0000 0000000000000000 " "Info: State \"\|key1\|scan_key.0000\" uses code string \"0000000000000000\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1110 0000000000000011 " "Info: State \"\|key1\|scan_key.1110\" uses code string \"0000000000000011\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1101 0000000000000101 " "Info: State \"\|key1\|scan_key.1101\" uses code string \"0000000000000101\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1100 0000000000001001 " "Info: State \"\|key1\|scan_key.1100\" uses code string \"0000000000001001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1011 0000000000010001 " "Info: State \"\|key1\|scan_key.1011\" uses code string \"0000000000010001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1010 0000000000100001 " "Info: State \"\|key1\|scan_key.1010\" uses code string \"0000000000100001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1001 0000000001000001 " "Info: State \"\|key1\|scan_key.1001\" uses code string \"0000000001000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1000 0000000010000001 " "Info: State \"\|key1\|scan_key.1000\" uses code string \"0000000010000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0111 0000000100000001 " "Info: State \"\|key1\|scan_key.0111\" uses code string \"0000000100000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0110 0000001000000001 " "Info: State \"\|key1\|scan_key.0110\" uses code string \"0000001000000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0101 0000010000000001 " "Info: State \"\|key1\|scan_key.0101\" uses code string \"0000010000000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0100 0000100000000001 " "Info: State \"\|key1\|scan_key.0100\" uses code string \"0000100000000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0011 0001000000000001 " "Info: State \"\|key1\|scan_key.0011\" uses code string \"0001000000000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0010 0010000000000001 " "Info: State \"\|key1\|scan_key.0010\" uses code string \"0010000000000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.0001 0100000000000001 " "Info: State \"\|key1\|scan_key.0001\" uses code string \"0100000000000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|key1\|scan_key.1111 1000000000000001 " "Info: State \"\|key1\|scan_key.1111\" uses code string \"1000000000000001\"" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] VCC " "Warning: Pin \"en\[1\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] VCC " "Warning: Pin \"en\[2\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] VCC " "Warning: Pin \"en\[3\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] VCC " "Warning: Pin \"en\[4\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] VCC " "Warning: Pin \"en\[5\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] VCC " "Warning: Pin \"en\[6\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] VCC " "Warning: Pin \"en\[7\]\" stuck at VCC" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } { "key1.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "92 " "Info: Implemented 92 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "66 " "Info: Implemented 66 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 15:56:24 2006 " "Info: Processing ended: Sat Oct 21 15:56:24 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}