key1.tan.qmsg

来自「FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 15:56:31 2006 " "Info: Processing ended: Sat Oct 21 15:56:31 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}