key1.hier_info

FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

|key1
clk => row[2]~reg0.CLK
clk => row[1]~reg0.CLK
clk => row[0]~reg0.CLK
clk => cnt_scan[15].CLK
clk => cnt_scan[14].CLK
clk => cnt_scan[13].CLK
clk => cnt_scan[12].CLK
clk => cnt_scan[11].CLK
clk => cnt_scan[10].CLK
clk => cnt_scan[9].CLK
clk => cnt_scan[8].CLK
clk => cnt_scan[7].CLK
clk => cnt_scan[6].CLK
clk => cnt_scan[5].CLK
clk => cnt_scan[4].CLK
clk => cnt_scan[3].CLK
clk => cnt_scan[2].CLK
clk => cnt_scan[1].CLK
clk => cnt_scan[0].CLK
clk => row[3]~reg0.CLK
clk => scan_key~16.IN1
rst => row[2]~reg0.PRESET
rst => row[1]~reg0.PRESET
rst => row[0]~reg0.ACLR
rst => cnt_scan[15].ACLR
rst => cnt_scan[14].ACLR
rst => cnt_scan[13].ACLR
rst => cnt_scan[12].ACLR
rst => cnt_scan[11].ACLR
rst => cnt_scan[10].ACLR
rst => cnt_scan[9].ACLR
rst => cnt_scan[8].ACLR
rst => cnt_scan[7].ACLR
rst => cnt_scan[6].ACLR
rst => cnt_scan[5].ACLR
rst => cnt_scan[4].ACLR
rst => cnt_scan[3].ACLR
rst => cnt_scan[2].ACLR
rst => cnt_scan[1].ACLR
rst => cnt_scan[0].ACLR
rst => row[3]~reg0.PRESET
rst => scan_key~17.IN1
row[0] <= row[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
row[1] <= row[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
row[2] <= row[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
row[3] <= row[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
column[0] => Decoder~0.IN3
column[1] => Decoder~0.IN2
column[2] => Decoder~0.IN1
column[3] => Decoder~0.IN0
dataout[0] <= <VCC>
dataout[1] <= reduce_or~13.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= reduce_or~12.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= reduce_or~11.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= reduce_or~10.DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= reduce_or~9.DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= reduce_or~8.DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= reduce_or~7.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <VCC>
en[2] <= <VCC>
en[3] <= <VCC>
en[4] <= <VCC>
en[5] <= <VCC>
en[6] <= <VCC>
en[7] <= <VCC>