traffic.tan.qmsg

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。综合实验的源码。包括交通灯实验等。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register second\[2\] register first\[3\] 247.95 MHz 4.033 ns Internal " "Info: Clock \"clk\" has Internal fmax of 247.95 MHz between source register \"second\[2\]\" and destination register \"first\[3\]\" (period= 4.033 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.772 ns + Longest register register " "Info: + Longest register to register delay is 3.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second\[2\] 1 REG LC_X22_Y16_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y16_N7; Fanout = 4; REG Node = 'second\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { second[2] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.546 ns) + CELL(0.590 ns) 1.136 ns rtl~1 2 COMB LC_X22_Y16_N8 9 " "Info: 2: + IC(0.546 ns) + CELL(0.590 ns) = 1.136 ns; Loc. = LC_X22_Y16_N8; Fanout = 9; COMB Node = 'rtl~1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "1.136 ns" { second[2] rtl~1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.781 ns) + CELL(0.114 ns) 2.031 ns first\[3\]~396 3 COMB LC_X21_Y16_N2 4 " "Info: 3: + IC(0.781 ns) + CELL(0.114 ns) = 2.031 ns; Loc. = LC_X21_Y16_N2; Fanout = 4; COMB Node = 'first\[3\]~396'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "0.895 ns" { rtl~1 first[3]~396 } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(1.225 ns) 3.772 ns first\[3\] 4 REG LC_X21_Y16_N5 4 " "Info: 4: + IC(0.516 ns) + CELL(1.225 ns) = 3.772 ns; Loc. = LC_X21_Y16_N5; Fanout = 4; REG Node = 'first\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "1.741 ns" { first[3]~396 first[3] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 51.14 % ) " "Info: Total cell delay = 1.929 ns ( 51.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.843 ns ( 48.86 % ) " "Info: Total interconnect delay = 1.843 ns ( 48.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "3.772 ns" { second[2] rtl~1 first[3]~396 first[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.772 ns" { second[2] rtl~1 first[3]~396 first[3] } { 0.000ns 0.546ns 0.781ns 0.516ns } { 0.000ns 0.590ns 0.114ns 1.225ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.828 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 11.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_48 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.165 ns) + CELL(0.935 ns) 7.569 ns div_cnt\[24\] 2 REG LC_X8_Y10_N7 11 " "Info: 2: + IC(5.165 ns) + CELL(0.935 ns) = 7.569 ns; Loc. = LC_X8_Y10_N7; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "6.100 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 11.828 ns first\[3\] 3 REG LC_X21_Y16_N5 4 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 11.828 ns; Loc. = LC_X21_Y16_N5; Fanout = 4; REG Node = 'first\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "4.259 ns" { div_cnt[24] first[3] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 26.34 % ) " "Info: Total cell delay = 3.115 ns ( 26.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.713 ns ( 73.66 % ) " "Info: Total interconnect delay = 8.713 ns ( 73.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "11.828 ns" { clk div_cnt[24] first[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.828 ns" { clk clk~out0 div_cnt[24] first[3] } { 0.000ns 0.000ns 5.165ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.828 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 11.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_48 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.165 ns) + CELL(0.935 ns) 7.569 ns div_cnt\[24\] 2 REG LC_X8_Y10_N7 11 " "Info: 2: + IC(5.165 ns) + CELL(0.935 ns) = 7.569 ns; Loc. = LC_X8_Y10_N7; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "6.100 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 11.828 ns second\[2\] 3 REG LC_X22_Y16_N7 4 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 11.828 ns; Loc. = LC_X22_Y16_N7; Fanout = 4; REG Node = 'second\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "4.259 ns" { div_cnt[24] second[2] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 26.34 % ) " "Info: Total cell delay = 3.115 ns ( 26.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.713 ns ( 73.66 % ) " "Info: Total interconnect delay = 8.713 ns ( 73.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "11.828 ns" { clk div_cnt[24] second[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.828 ns" { clk clk~out0 div_cnt[24] second[2] } { 0.000ns 0.000ns 5.165ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "11.828 ns" { clk div_cnt[24] first[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.828 ns" { clk clk~out0 div_cnt[24] first[3] } { 0.000ns 0.000ns 5.165ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "11.828 ns" { clk div_cnt[24] second[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.828 ns" { clk clk~out0 div_cnt[24] second[2] } { 0.000ns 0.000ns 5.165ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "3.772 ns" { second[2] rtl~1 first[3]~396 first[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.772 ns" { second[2] rtl~1 first[3]~396 first[3] } { 0.000ns 0.546ns 0.781ns 0.516ns } { 0.000ns 0.590ns 0.114ns 1.225ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "11.828 ns" { clk div_cnt[24] first[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.828 ns" { clk clk~out0 div_cnt[24] first[3] } { 0.000ns 0.000ns 5.165ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "11.828 ns" { clk div_cnt[24] second[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.828 ns" { clk clk~out0 div_cnt[24] second[2] } { 0.000ns 0.000ns 5.165ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lightG\[0\] state\[0\] 20.681 ns register " "Info: tco from clock \"clk\" to destination pin \"lightG\[0\]\" through register \"state\[0\]\" is 20.681 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.828 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_48 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { clk } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.165 ns) + CELL(0.935 ns) 7.569 ns div_cnt\[24\] 2 REG LC_X8_Y10_N7 11 " "Info: 2: + IC(5.165 ns) + CELL(0.935 ns) = 7.569 ns; Loc. = LC_X8_Y10_N7; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "6.100 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 11.828 ns state\[0\] 3 REG LC_X23_Y16_N5 12 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 11.828 ns; Loc. = LC_X23_Y16_N5; Fanout = 12; REG Node = 'state\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "4.259 ns" { div_cnt[24] state[0] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 26.34 % ) " "Info: Total cell delay = 3.115 ns ( 26.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.713 ns ( 73.66 % ) " "Info: Total interconnect delay = 8.713 ns ( 73.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "11.828 ns" { clk div_cnt[24] state[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.828 ns" { clk clk~out0 div_cnt[24] state[0] } { 0.000ns 0.000ns 5.165ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.629 ns + Longest register pin " "Info: + Longest register to pin delay is 8.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\] 1 REG LC_X23_Y16_N5 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y16_N5; Fanout = 12; REG Node = 'state\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "" { state[0] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(0.114 ns) 1.764 ns Mux~479 2 COMB LC_X21_Y15_N2 4 " "Info: 2: + IC(1.650 ns) + CELL(0.114 ns) = 1.764 ns; Loc. = LC_X21_Y15_N2; Fanout = 4; COMB Node = 'Mux~479'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "1.764 ns" { state[0] Mux~479 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.757 ns) + CELL(2.108 ns) 8.629 ns lightG\[0\] 3 PIN PIN_79 0 " "Info: 3: + IC(4.757 ns) + CELL(2.108 ns) = 8.629 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'lightG\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "6.865 ns" { Mux~479 lightG[0] } "NODE_NAME" } "" } } { "traffic.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/traffic.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.222 ns ( 25.75 % ) " "Info: Total cell delay = 2.222 ns ( 25.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.407 ns ( 74.25 % ) " "Info: Total interconnect delay = 6.407 ns ( 74.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "8.629 ns" { state[0] Mux~479 lightG[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.629 ns" { state[0] Mux~479 lightG[0] } { 0.000ns 1.650ns 4.757ns } { 0.000ns 0.114ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "11.828 ns" { clk div_cnt[24] state[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.828 ns" { clk clk~out0 div_cnt[24] state[0] } { 0.000ns 0.000ns 5.165ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/db/traffic.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/综合实验/交通灯/traffic/" "" "8.629 ns" { state[0] Mux~479 lightG[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.629 ns" { state[0] Mux~479 lightG[0] } { 0.000ns 1.650ns 4.757ns } { 0.000ns 0.114ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 29 15:03:52 2006 " "Info: Processing ended: Fri Sep 29 15:03:52 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}