seg70.map.qmsg

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 14 17:50:55 2006 " "Info: Processing started: Thu Sep 14 17:50:55 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seg70 -c seg70 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg70 -c seg70" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg70.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg70.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg70-arch " "Info: Found design unit 1: seg70-arch" {  } { { "seg70.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/7段数码管/seg70/seg70.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seg70 " "Info: Found entity 1: seg70" {  } { { "seg70.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/7段数码管/seg70/seg70.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seg70 " "Info: Elaborating entity \"seg70\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "seg70.vhd(43) " "Info (10425): VHDL Case Statement information at seg70.vhd(43): OTHERS choice is never selected" {  } { { "seg70.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/7段数码管/seg70/seg70.vhd" 43 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "seg70.vhd(98) " "Info (10425): VHDL Case Statement information at seg70.vhd(98): OTHERS choice is never selected" {  } { { "seg70.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/7段数码管/seg70/seg70.vhd" 98 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "seg70.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/7段数码管/seg70/seg70.vhd" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "48 " "Info: Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "30 " "Info: Implemented 30 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 14 17:50:56 2006 " "Info: Processing ended: Thu Sep 14 17:50:56 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}