seg73.tan.qmsg

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 11 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "first_over " "Info: Detected ripple clock \"first_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 26 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "first_over" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[24\] " "Info: Detected ripple clock \"div_cnt\[24\]\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 37 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div_cnt\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "third_over " "Info: Detected ripple clock \"third_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 28 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "third_over" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second_over " "Info: Detected ripple clock \"second_over\" as buffer" {  } { { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "second_over" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register last_over register cntfirst\[1\] 62.06 MHz 16.114 ns Internal " "Info: Clock \"clk\" has Internal fmax of 62.06 MHz between source register \"last_over\" and destination register \"cntfirst\[1\]\" (period= 16.114 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.496 ns + Longest register register " "Info: + Longest register to register delay is 1.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns last_over 1 REG LC_X16_Y10_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y10_N3; Fanout = 3; REG Node = 'last_over'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "" { last_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.575 ns) + CELL(0.114 ns) 0.689 ns process1~0 2 COMB LC_X16_Y10_N0 3 " "Info: 2: + IC(0.575 ns) + CELL(0.114 ns) = 0.689 ns; Loc. = LC_X16_Y10_N0; Fanout = 3; COMB Node = 'process1~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "0.689 ns" { last_over process1~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.309 ns) 1.496 ns cntfirst\[1\] 3 REG LC_X16_Y10_N5 5 " "Info: 3: + IC(0.498 ns) + CELL(0.309 ns) = 1.496 ns; Loc. = LC_X16_Y10_N5; Fanout = 5; REG Node = 'cntfirst\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "0.807 ns" { process1~0 cntfirst[1] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.423 ns ( 28.28 % ) " "Info: Total cell delay = 0.423 ns ( 28.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.073 ns ( 71.72 % ) " "Info: Total interconnect delay = 1.073 ns ( 71.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "1.496 ns" { last_over process1~0 cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.496 ns" { last_over process1~0 cntfirst[1] } { 0.000ns 0.575ns 0.498ns } { 0.000ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-14.357 ns - Smallest " "Info: - Smallest clock skew is -14.357 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.383 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 29; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "" { clk } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns div_cnt\[24\] 2 REG LC_X27_Y10_N7 6 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N7; Fanout = 6; REG Node = 'div_cnt\[24\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "1.697 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.506 ns) + CELL(0.711 ns) 7.383 ns cntfirst\[1\] 3 REG LC_X16_Y10_N5 5 " "Info: 3: + IC(3.506 ns) + CELL(0.711 ns) = 7.383 ns; Loc. = LC_X16_Y10_N5; Fanout = 5; REG Node = 'cntfirst\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.217 ns" { div_cnt[24] cntfirst[1] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.19 % ) " "Info: Total cell delay = 3.115 ns ( 42.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.268 ns ( 57.81 % ) " "Info: Total interconnect delay = 4.268 ns ( 57.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "7.383 ns" { clk div_cnt[24] cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.383 ns" { clk clk~out0 div_cnt[24] cntfirst[1] } { 0.000ns 0.000ns 0.762ns 3.506ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 21.740 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 21.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 29; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "" { clk } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns div_cnt\[24\] 2 REG LC_X27_Y10_N7 6 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N7; Fanout = 6; REG Node = 'div_cnt\[24\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "1.697 ns" { clk div_cnt[24] } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.506 ns) + CELL(0.935 ns) 7.607 ns first_over 3 REG LC_X16_Y10_N0 5 " "Info: 3: + IC(3.506 ns) + CELL(0.935 ns) = 7.607 ns; Loc. = LC_X16_Y10_N0; Fanout = 5; REG Node = 'first_over'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.441 ns" { div_cnt[24] first_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.534 ns) + CELL(0.935 ns) 13.076 ns second_over 4 REG LC_X8_Y10_N6 5 " "Info: 4: + IC(4.534 ns) + CELL(0.935 ns) = 13.076 ns; Loc. = LC_X8_Y10_N6; Fanout = 5; REG Node = 'second_over'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "5.469 ns" { first_over second_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 17.520 ns third_over 5 REG LC_X8_Y10_N7 5 " "Info: 5: + IC(3.509 ns) + CELL(0.935 ns) = 17.520 ns; Loc. = LC_X8_Y10_N7; Fanout = 5; REG Node = 'third_over'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.444 ns" { second_over third_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.711 ns) 21.740 ns last_over 6 REG LC_X16_Y10_N3 3 " "Info: 6: + IC(3.509 ns) + CELL(0.711 ns) = 21.740 ns; Loc. = LC_X16_Y10_N3; Fanout = 3; REG Node = 'last_over'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "4.220 ns" { third_over last_over } "NODE_NAME" } "" } } { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.920 ns ( 27.23 % ) " "Info: Total cell delay = 5.920 ns ( 27.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.820 ns ( 72.77 % ) " "Info: Total interconnect delay = 15.820 ns ( 72.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "21.740 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.740 ns" { clk clk~out0 div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 0.762ns 3.506ns 4.534ns 3.509ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "7.383 ns" { clk div_cnt[24] cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.383 ns" { clk clk~out0 div_cnt[24] cntfirst[1] } { 0.000ns 0.000ns 0.762ns 3.506ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "21.740 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.740 ns" { clk clk~out0 div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 0.762ns 3.506ns 4.534ns 3.509ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "seg73.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "1.496 ns" { last_over process1~0 cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.496 ns" { last_over process1~0 cntfirst[1] } { 0.000ns 0.575ns 0.498ns } { 0.000ns 0.114ns 0.309ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "7.383 ns" { clk div_cnt[24] cntfirst[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.383 ns" { clk clk~out0 div_cnt[24] cntfirst[1] } { 0.000ns 0.000ns 0.762ns 3.506ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seg73" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/db/seg73.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/7段数码管/seg73/" "" "21.740 ns" { clk div_cnt[24] first_over second_over third_over last_over } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.740 ns" { clk clk~out0 div_cnt[24] first_over second_over third_over last_over } { 0.000ns 0.000ns 0.762ns 3.506ns 4.534ns 3.509ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}