lcd.tan.qmsg

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[0\] state\[2\] 34.748 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[0\]\" through register \"state\[2\]\" is 34.748 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 17.777 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 17.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkcnt\[18\] 2 REG LC_X11_Y10_N9 2 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X11_Y10_N9; Fanout = 2; REG Node = 'clkcnt\[18\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.680 ns" { clk clkcnt[18] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.590 ns) 4.267 ns rtl~491 3 COMB LC_X11_Y10_N6 1 " "Info: 3: + IC(0.528 ns) + CELL(0.590 ns) = 4.267 ns; Loc. = LC_X11_Y10_N6; Fanout = 1; COMB Node = 'rtl~491'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.118 ns" { clkcnt[18] rtl~491 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.590 ns) 6.083 ns rtl~495 4 COMB LC_X11_Y13_N8 1 " "Info: 4: + IC(1.226 ns) + CELL(0.590 ns) = 6.083 ns; Loc. = LC_X11_Y13_N8; Fanout = 1; COMB Node = 'rtl~495'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.816 ns" { rtl~491 rtl~495 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 6.379 ns rtl~10 5 COMB LC_X11_Y13_N9 10 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 6.379 ns; Loc. = LC_X11_Y13_N9; Fanout = 10; COMB Node = 'rtl~10'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.296 ns" { rtl~495 rtl~10 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.935 ns) 8.674 ns clkdiv 6 REG LC_X11_Y10_N4 3 " "Info: 6: + IC(1.360 ns) + CELL(0.935 ns) = 8.674 ns; Loc. = LC_X11_Y10_N4; Fanout = 3; REG Node = 'clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "2.295 ns" { rtl~10 clkdiv } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.909 ns) + CELL(0.935 ns) 13.518 ns clk_int 7 REG LC_X8_Y10_N2 20 " "Info: 7: + IC(3.909 ns) + CELL(0.935 ns) = 13.518 ns; Loc. = LC_X8_Y10_N2; Fanout = 20; REG Node = 'clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.844 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显