lcd.tan.qmsg

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 93 " "Warning: Circuit may not operate. Detected 93 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "state\[2\] state\[2\] clk 2.001 ns " "Info: Found hold time violation between source  pin or register \"state\[2\]\" and destination pin or register \"state\[2\]\" for clock \"clk\" (Hold time is 2.001 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.823 ns + Largest " "Info: + Largest clock skew is 2.823 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 17.777 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 17.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkcnt\[18\] 2 REG LC_X11_Y10_N9 2 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X11_Y10_N9; Fanout = 2; REG Node = 'clkcnt\[18\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.680 ns" { clk clkcnt[18] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.590 ns) 4.267 ns rtl~491 3 COMB LC_X11_Y10_N6 1 " "Info: 3: + IC(0.528 ns) + CELL(0.590 ns) = 4.267 ns; Loc. = LC_X11_Y10_N6; Fanout = 1; COMB Node = 'rtl~491'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.118 ns" { clkcnt[18] rtl~491 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.590 ns) 6.083 ns rtl~495 4 COMB LC_X11_Y13_N8 1 " "Info: 4: + IC(1.226 ns) + CELL(0.590 ns) = 6.083 ns; Loc. = LC_X11_Y13_N8; Fanout = 1; COMB Node = 'rtl~495'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.816 ns" { rtl~491 rtl~495 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 6.379 ns rtl~10 5 COMB LC_X11_Y13_N9 10 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 6.379 ns; Loc. = LC_X11_Y13_N9; Fanout = 10; COMB Node = 'rtl~10'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.296 ns" { rtl~495 rtl~10 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.935 ns) 8.674 ns clkdiv 6 REG LC_X11_Y10_N4 3 " "Info: 6: + IC(1.360 ns) + CELL(0.935 ns) = 8.674 ns; Loc. = LC_X11_Y10_N4; Fanout = 3; REG Node = 'clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "2.295 ns" { rtl~10 clkdiv } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.909 ns) + CELL(0.935 ns) 13.518 ns clk_int 7 REG LC_X8_Y10_N2 20 " "Info: 7: + IC(3.909 ns) + CELL(0.935 ns) = 13.518 ns; Loc. = LC_X8_Y10_N2; Fanout = 20; REG Node = 'clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.844 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 17.777 ns state\[2\] 8 REG LC_X23_Y16_N5 11 " "Info: 8: + IC(3.548 ns) + CELL(0.711 ns) = 17.777 ns; Loc. = LC_X23_Y16_N5; Fanout = 11; REG Node = 'state\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.259 ns" { clk_int state[2] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.279 ns ( 35.32 % ) " "Info: Total cell delay = 6.279 ns ( 35.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.498 ns ( 64.68 % ) " "Info: Total interconnect delay = 11.498 ns ( 64.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "17.777 ns" { clk clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.777 ns" { clk clk~out0 clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[2] } { 0.000ns 0.000ns 0.745ns 0.528ns 1.226ns 0.182ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.114ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 14.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 14.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.935 ns) 3.178 ns clkcnt\[2\] 2 REG LC_X11_Y13_N9 4 " "Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X11_Y13_N9; Fanout = 4; REG Node = 'clkcnt\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.709 ns" { clk clkcnt[2] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 3.556 ns rtl~10 3 COMB LC_X11_Y13_N9 10 " "Info: 3: + IC(0.000 ns) + CELL(0.378 ns) = 3.556 ns; Loc. = LC_X11_Y13_N9; Fanout = 10; COMB Node = 'rtl~10'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.378 ns" { clkcnt[2] rtl~10 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.935 ns) 5.851 ns clkdiv 4 REG LC_X11_Y10_N4 3 " "Info: 4: + IC(1.360 ns) + CELL(0.935 ns) = 5.851 ns; Loc. = LC_X11_Y10_N4; Fanout = 3; REG Node = 'clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "2.295 ns" { rtl~10 clkdiv } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.909 ns) + CELL(0.935 ns) 10.695 ns clk_int 5 REG LC_X8_Y10_N2 20 " "Info: 5: + IC(3.909 ns) + CELL(0.935 ns) = 10.695 ns; Loc. = LC_X8_Y10_N2; Fanout = 20; REG Node = 'clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.844 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 14.954 ns state\[2\] 6 REG LC_X23_Y16_N5 11 " "Info: 6: + IC(3.548 ns) + CELL(0.711 ns) = 14.954 ns; Loc. = LC_X23_Y16_N5; Fanout = 11; REG Node = 'state\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.259 ns" { clk_int state[2] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.363 ns ( 35.86 % ) " "Info: Total cell delay = 5.363 ns ( 35.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.591 ns ( 64.14 % ) " "Info: Total interconnect delay = 9.591 ns ( 64.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "14.954 ns" { clk clkcnt[2] rtl~10 clkdiv clk_int state[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.954 ns" { clk clk~out0 clkcnt[2] rtl~10 clkdiv clk_int state[2] } { 0.000ns 0.000ns 0.774ns 0.000ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "17.777 ns" { clk clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.777 ns" { clk clk~out0 clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[2] } { 0.000ns 0.000ns 0.745ns 0.528ns 1.226ns 0.182ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "14.954 ns" { clk clkcnt[2] rtl~10 clkdiv clk_int state[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.954 ns" { clk clk~out0 clkcnt[2] rtl~10 clkdiv clk_int state[2] } { 0.000ns 0.000ns 0.774ns 0.000ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.613 ns - Shortest register register " "Info: - Shortest register to register delay is 0.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[2\] 1 REG LC_X23_Y16_N5 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y16_N5; Fanout = 11; REG Node = 'state\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "" { state[2] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.613 ns) 0.613 ns state\[2\] 2 REG LC_X23_Y16_N5 11 " "Info: 2: + IC(0.000 ns) + CELL(0.613 ns) = 0.613 ns; Loc. = LC_X23_Y16_N5; Fanout = 11; REG Node = 'state\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.613 ns" { state[2] state[2] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.613 ns ( 100.00 % ) " "Info: Total cell delay = 0.613 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.613 ns" { state[2] state[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.613 ns" { state[2] state[2] } { 0.000ns 0.000ns } { 0.000ns 0.613ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "17.777 ns" { clk clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.777 ns" { clk clk~out0 clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[2] } { 0.000ns 0.000ns 0.745ns 0.528ns 1.226ns 0.182ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "14.954 ns" { clk clkcnt[2] rtl~10 clkdiv clk_int state[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.954 ns" { clk clk~out0 clkcnt[2] rtl~10 clkdiv clk_int state[2] } { 0.000ns 0.000ns 0.774ns 0.000ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.613 ns" { state[2] state[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.613 ns" { state[2] state[2] } { 0.000ns 0.000ns } { 0.000ns 0.613ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}