lcd.tan.qmsg

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "26 " "Warning: Found 26 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[2\] " "Info: Detected ripple clock \"clkcnt\[2\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[5\] " "Info: Detected ripple clock \"clkcnt\[5\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~494 " "Info: Detected gated clock \"rtl~494\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~494" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[3\] " "Info: Detected ripple clock \"clkcnt\[3\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[4\] " "Info: Detected ripple clock \"clkcnt\[4\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[6\] " "Info: Detected ripple clock \"clkcnt\[6\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[9\] " "Info: Detected ripple clock \"clkcnt\[9\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~493 " "Info: Detected gated clock \"rtl~493\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~493" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[7\] " "Info: Detected ripple clock \"clkcnt\[7\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[8\] " "Info: Detected ripple clock \"clkcnt\[8\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[10\] " "Info: Detected ripple clock \"clkcnt\[10\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[14\] " "Info: Detected ripple clock \"clkcnt\[14\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~492 " "Info: Detected gated clock \"rtl~492\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~492" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[13\] " "Info: Detected ripple clock \"clkcnt\[13\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[11\] " "Info: Detected ripple clock \"clkcnt\[11\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[12\] " "Info: Detected ripple clock \"clkcnt\[12\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~491 " "Info: Detected gated clock \"rtl~491\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~491" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[15\] " "Info: Detected ripple clock \"clkcnt\[15\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[16\] " "Info: Detected ripple clock \"clkcnt\[16\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[16\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[17\] " "Info: Detected ripple clock \"clkcnt\[17\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[17\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[0\] " "Info: Detected ripple clock \"clkcnt\[0\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[1\] " "Info: Detected ripple clock \"clkcnt\[1\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[18\] " "Info: Detected ripple clock \"clkcnt\[18\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[18\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~10 " "Info: Detected gated clock \"rtl~10\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv " "Info: Detected ripple clock \"clkdiv\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkdiv" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_int " "Info: Detected ripple clock \"clk_int\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 71 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register state\[4\] register counter\[4\] 131.15 MHz 7.625 ns Internal " "Info: Clock \"clk\" has Internal fmax of 131.15 MHz between source register \"state\[4\]\" and destination register \"counter\[4\]\" (period= 7.625 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.541 ns + Longest register register " "Info: + Longest register to register delay is 4.541 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[4\] 1 REG LC_X24_Y16_N0 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y16_N0; Fanout = 10; REG Node = 'state\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "" { state[4] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.170 ns) + CELL(0.114 ns) 1.284 ns rtl~488 2 COMB LC_X23_Y16_N8 9 " "Info: 2: + IC(1.170 ns) + CELL(0.114 ns) = 1.284 ns; Loc. = LC_X23_Y16_N8; Fanout = 9; COMB Node = 'rtl~488'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.284 ns" { state[4] rtl~488 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.292 ns) 2.074 ns rtl~4 3 COMB LC_X23_Y16_N0 7 " "Info: 3: + IC(0.498 ns) + CELL(0.292 ns) = 2.074 ns; Loc. = LC_X23_Y16_N0; Fanout = 7; COMB Node = 'rtl~4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.790 ns" { rtl~488 rtl~4 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.442 ns) 3.218 ns counter\[0\]~326 4 COMB LC_X24_Y16_N8 7 " "Info: 4: + IC(0.702 ns) + CELL(0.442 ns) = 3.218 ns; Loc. = LC_X24_Y16_N8; Fanout = 7; COMB Node = 'counter\[0\]~326'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.144 ns" { rtl~4 counter[0]~326 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.867 ns) 4.541 ns counter\[4\] 5 REG LC_X24_Y16_N5 15 " "Info: 5: + IC(0.456 ns) + CELL(0.867 ns) = 4.541 ns; Loc. = LC_X24_Y16_N5; Fanout = 15; REG Node = 'counter\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.323 ns" { counter[0]~326 counter[4] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.715 ns ( 37.77 % ) " "Info: Total cell delay = 1.715 ns ( 37.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.826 ns ( 62.23 % ) " "Info: Total interconnect delay = 2.826 ns ( 62.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.541 ns" { state[4] rtl~488 rtl~4 counter[0]~326 counter[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.541 ns" { state[4] rtl~488 rtl~4 counter[0]~326 counter[4] } { 0.000ns 1.170ns 0.498ns 0.702ns 0.456ns } { 0.000ns 0.114ns 0.292ns 0.442ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.823 ns - Smallest " "Info: - Smallest clock skew is -2.823 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 14.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 14.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.935 ns) 3.178 ns clkcnt\[2\] 2 REG LC_X11_Y13_N9 4 " "Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X11_Y13_N9; Fanout = 4; REG Node = 'clkcnt\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.709 ns" { clk clkcnt[2] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 3.556 ns rtl~10 3 COMB LC_X11_Y13_N9 10 " "Info: 3: + IC(0.000 ns) + CELL(0.378 ns) = 3.556 ns; Loc. = LC_X11_Y13_N9; Fanout = 10; COMB Node = 'rtl~10'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.378 ns" { clkcnt[2] rtl~10 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.935 ns) 5.851 ns clkdiv 4 REG LC_X11_Y10_N4 3 " "Info: 4: + IC(1.360 ns) + CELL(0.935 ns) = 5.851 ns; Loc. = LC_X11_Y10_N4; Fanout = 3; REG Node = 'clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "2.295 ns" { rtl~10 clkdiv } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.909 ns) + CELL(0.935 ns) 10.695 ns clk_int 5 REG LC_X8_Y10_N2 20 " "Info: 5: + IC(3.909 ns) + CELL(0.935 ns) = 10.695 ns; Loc. = LC_X8_Y10_N2; Fanout = 20; REG Node = 'clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.844 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 14.954 ns counter\[4\] 6 REG LC_X24_Y16_N5 15 " "Info: 6: + IC(3.548 ns) + CELL(0.711 ns) = 14.954 ns; Loc. = LC_X24_Y16_N5; Fanout = 15; REG Node = 'counter\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.259 ns" { clk_int counter[4] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.363 ns ( 35.86 % ) " "Info: Total cell delay = 5.363 ns ( 35.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.591 ns ( 64.14 % ) " "Info: Total interconnect delay = 9.591 ns ( 64.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "14.954 ns" { clk clkcnt[2] rtl~10 clkdiv clk_int counter[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.954 ns" { clk clk~out0 clkcnt[2] rtl~10 clkdiv clk_int counter[4] } { 0.000ns 0.000ns 0.774ns 0.000ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 17.777 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 17.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkcnt\[18\] 2 REG LC_X11_Y10_N9 2 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X11_Y10_N9; Fanout = 2; REG Node = 'clkcnt\[18\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.680 ns" { clk clkcnt[18] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.590 ns) 4.267 ns rtl~491 3 COMB LC_X11_Y10_N6 1 " "Info: 3: + IC(0.528 ns) + CELL(0.590 ns) = 4.267 ns; Loc. = LC_X11_Y10_N6; Fanout = 1; COMB Node = 'rtl~491'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.118 ns" { clkcnt[18] rtl~491 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.590 ns) 6.083 ns rtl~495 4 COMB LC_X11_Y13_N8 1 " "Info: 4: + IC(1.226 ns) + CELL(0.590 ns) = 6.083 ns; Loc. = LC_X11_Y13_N8; Fanout = 1; COMB Node = 'rtl~495'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "1.816 ns" { rtl~491 rtl~495 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 6.379 ns rtl~10 5 COMB LC_X11_Y13_N9 10 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 6.379 ns; Loc. = LC_X11_Y13_N9; Fanout = 10; COMB Node = 'rtl~10'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "0.296 ns" { rtl~495 rtl~10 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.935 ns) 8.674 ns clkdiv 6 REG LC_X11_Y10_N4 3 " "Info: 6: + IC(1.360 ns) + CELL(0.935 ns) = 8.674 ns; Loc. = LC_X11_Y10_N4; Fanout = 3; REG Node = 'clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "2.295 ns" { rtl~10 clkdiv } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.909 ns) + CELL(0.935 ns) 13.518 ns clk_int 7 REG LC_X8_Y10_N2 20 " "Info: 7: + IC(3.909 ns) + CELL(0.935 ns) = 13.518 ns; Loc. = LC_X8_Y10_N2; Fanout = 20; REG Node = 'clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.844 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 17.777 ns state\[4\] 8 REG LC_X24_Y16_N0 10 " "Info: 8: + IC(3.548 ns) + CELL(0.711 ns) = 17.777 ns; Loc. = LC_X24_Y16_N0; Fanout = 10; REG Node = 'state\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.259 ns" { clk_int state[4] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.279 ns ( 35.32 % ) " "Info: Total cell delay = 6.279 ns ( 35.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.498 ns ( 64.68 % ) " "Info: Total interconnect delay = 11.498 ns ( 64.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "17.777 ns" { clk clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.777 ns" { clk clk~out0 clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[4] } { 0.000ns 0.000ns 0.745ns 0.528ns 1.226ns 0.182ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.114ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "14.954 ns" { clk clkcnt[2] rtl~10 clkdiv clk_int counter[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.954 ns" { clk clk~out0 clkcnt[2] rtl~10 clkdiv clk_int counter[4] } { 0.000ns 0.000ns 0.774ns 0.000ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "17.777 ns" { clk clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.777 ns" { clk clk~out0 clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[4] } { 0.000ns 0.000ns 0.745ns 0.528ns 1.226ns 0.182ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.114ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "lcd.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "4.541 ns" { state[4] rtl~488 rtl~4 counter[0]~326 counter[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.541 ns" { state[4] rtl~488 rtl~4 counter[0]~326 counter[4] } { 0.000ns 1.170ns 0.498ns 0.702ns 0.456ns } { 0.000ns 0.114ns 0.292ns 0.442ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "14.954 ns" { clk clkcnt[2] rtl~10 clkdiv clk_int counter[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.954 ns" { clk clk~out0 clkcnt[2] rtl~10 clkdiv clk_int counter[4] } { 0.000ns 0.000ns 0.774ns 0.000ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/db/lcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/1602lcd液晶显示/lcd/" "" "17.777 ns" { clk clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.777 ns" { clk clk~out0 clkcnt[18] rtl~491 rtl~495 rtl~10 clkdiv clk_int state[4] } { 0.000ns 0.000ns 0.745ns 0.528ns 1.226ns 0.182ns 1.360ns 3.909ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.590ns 0.114ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}