lcd.hier_info

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

|lcd
clk => clkcnt[17].CLK
clk => clkcnt[16].CLK
clk => clkcnt[15].CLK
clk => clkcnt[14].CLK
clk => clkcnt[13].CLK
clk => clkcnt[12].CLK
clk => clkcnt[11].CLK
clk => clkcnt[10].CLK
clk => clkcnt[9].CLK
clk => clkcnt[8].CLK
clk => clkcnt[7].CLK
clk => clkcnt[6].CLK
clk => clkcnt[5].CLK
clk => clkcnt[4].CLK
clk => clkcnt[3].CLK
clk => clkcnt[2].CLK
clk => clkcnt[1].CLK
clk => clkcnt[0].CLK
clk => clkcnt[18].CLK
Reset => clkcnt[17].ACLR
Reset => clkcnt[16].ACLR
Reset => clkcnt[15].ACLR
Reset => clkcnt[14].ACLR
Reset => clkcnt[13].ACLR
Reset => clkcnt[12].ACLR
Reset => clkcnt[11].ACLR
Reset => clkcnt[10].ACLR
Reset => clkcnt[9].ACLR
Reset => clkcnt[8].ACLR
Reset => clkcnt[7].ACLR
Reset => clkcnt[6].ACLR
Reset => clkcnt[5].ACLR
Reset => clkcnt[4].ACLR
Reset => clkcnt[3].ACLR
Reset => clkcnt[2].ACLR
Reset => clkcnt[1].ACLR
Reset => clkcnt[0].ACLR
Reset => lcd_e~reg0.ACLR
Reset => clkcnt[18].ACLR
Reset => clkdiv.ACLR
Reset => clk_int.ACLR
Reset => state[9].ACLR
Reset => state[8].ACLR
Reset => state[7].ACLR
Reset => state[6].ACLR
Reset => state[5].ACLR
Reset => state[4].ACLR
Reset => state[3].ACLR
Reset => state[2].ACLR
Reset => state[1].ACLR
Reset => state[0].ACLR
Reset => counter[6].ACLR
Reset => counter[5].ACLR
Reset => counter[4].ACLR
Reset => counter[3].ACLR
Reset => counter[2].ACLR
Reset => counter[1].ACLR
Reset => counter[0].ACLR
Reset => flag.ACLR
Reset => div_counter[3].ACLR
Reset => div_counter[2].ACLR
Reset => div_counter[1].ACLR
Reset => div_counter[0].ACLR
Reset => state[10].ACLR
lcd_rs <= lcd_rs~0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rw <= lcd_rw~7.DB_MAX_OUTPUT_PORT_TYPE
lcd_e <= lcd_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data~90.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data~80.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data~70.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data~60.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data~50.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data~40.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data~30.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data~20.DB_MAX_OUTPUT_PORT_TYPE


|lcd|char_ram:aa
address[0] => Mux~0.IN69
address[0] => Mux~1.IN69
address[0] => Mux~2.IN69
address[0] => Mux~3.IN69
address[0] => Mux~4.IN69
address[0] => Mux~5.IN69
address[0] => Mux~6.IN69
address[1] => Mux~0.IN68
address[1] => Mux~1.IN68
address[1] => Mux~2.IN68
address[1] => Mux~3.IN68
address[1] => Mux~4.IN68
address[1] => Mux~5.IN68
address[1] => Mux~6.IN68
address[2] => Mux~0.IN67
address[2] => Mux~1.IN67
address[2] => Mux~2.IN67
address[2] => Mux~3.IN67
address[2] => Mux~4.IN67
address[2] => Mux~5.IN67
address[2] => Mux~6.IN67
address[3] => Mux~0.IN66
address[3] => Mux~1.IN66
address[3] => Mux~2.IN66
address[3] => Mux~3.IN66
address[3] => Mux~4.IN66
address[3] => Mux~5.IN66
address[3] => Mux~6.IN66
address[4] => Mux~0.IN65
address[4] => Mux~1.IN65
address[4] => Mux~2.IN65
address[4] => Mux~3.IN65
address[4] => Mux~4.IN65
address[4] => Mux~5.IN65
address[4] => Mux~6.IN65
address[5] => Mux~0.IN64
address[5] => Mux~1.IN64
address[5] => Mux~2.IN64
address[5] => Mux~3.IN64
address[5] => Mux~4.IN64
address[5] => Mux~5.IN64
address[5] => Mux~6.IN64
data[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= <GND>