dial1.tan.qmsg

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt_scan\[15\] " "Info: Detected ripple clock \"cnt_scan\[15\]\" as buffer" {  } { { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "cnt_scan\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt_scan\[0\] cnt_scan\[13\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"cnt_scan\[0\]\" and destination register \"cnt_scan\[13\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.536 ns + Longest register register " "Info: + Longest register to register delay is 2.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_scan\[0\] 1 REG LC_X7_Y9_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y9_N2; Fanout = 3; REG Node = 'cnt_scan\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "" { cnt_scan[0] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.564 ns) 1.097 ns cnt_scan\[0\]~173 2 COMB LC_X7_Y9_N2 2 " "Info: 2: + IC(0.533 ns) + CELL(0.564 ns) = 1.097 ns; Loc. = LC_X7_Y9_N2; Fanout = 2; COMB Node = 'cnt_scan\[0\]~173'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "1.097 ns" { cnt_scan[0] cnt_scan[0]~173 } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.175 ns cnt_scan\[1\]~169 3 COMB LC_X7_Y9_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.175 ns; Loc. = LC_X7_Y9_N3; Fanout = 2; COMB Node = 'cnt_scan\[1\]~169'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "0.078 ns" { cnt_scan[0]~173 cnt_scan[1]~169 } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.353 ns cnt_scan\[2\]~165 4 COMB LC_X7_Y9_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 1.353 ns; Loc. = LC_X7_Y9_N4; Fanout = 6; COMB Node = 'cnt_scan\[2\]~165'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "0.178 ns" { cnt_scan[1]~169 cnt_scan[2]~165 } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.561 ns cnt_scan\[7\]~145 5 COMB LC_X7_Y9_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.208 ns) = 1.561 ns; Loc. = LC_X7_Y9_N9; Fanout = 6; COMB Node = 'cnt_scan\[7\]~145'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "0.208 ns" { cnt_scan[2]~165 cnt_scan[7]~145 } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.697 ns cnt_scan\[12\]~125 6 COMB LC_X7_Y8_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.697 ns; Loc. = LC_X7_Y8_N4; Fanout = 3; COMB Node = 'cnt_scan\[12\]~125'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "0.136 ns" { cnt_scan[7]~145 cnt_scan[12]~125 } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.536 ns cnt_scan\[13\] 7 REG LC_X7_Y8_N5 3 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 2.536 ns; Loc. = LC_X7_Y8_N5; Fanout = 3; REG Node = 'cnt_scan\[13\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "0.839 ns" { cnt_scan[12]~125 cnt_scan[13] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.003 ns ( 78.98 % ) " "Info: Total cell delay = 2.003 ns ( 78.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.533 ns ( 21.02 % ) " "Info: Total interconnect delay = 0.533 ns ( 21.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.536 ns" { cnt_scan[0] cnt_scan[0]~173 cnt_scan[1]~169 cnt_scan[2]~165 cnt_scan[7]~145 cnt_scan[12]~125 cnt_scan[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.536 ns" { cnt_scan[0] cnt_scan[0]~173 cnt_scan[1]~169 cnt_scan[2]~165 cnt_scan[7]~145 cnt_scan[12]~125 cnt_scan[13] } { 0.000ns 0.533ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "" { clk } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns cnt_scan\[13\] 2 REG LC_X7_Y8_N5 3 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X7_Y8_N5; Fanout = 3; REG Node = 'cnt_scan\[13\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "1.434 ns" { clk cnt_scan[13] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.09 % ) " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.903 ns" { clk cnt_scan[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt_scan[13] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "" { clk } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns cnt_scan\[0\] 2 REG LC_X7_Y9_N2 3 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X7_Y9_N2; Fanout = 3; REG Node = 'cnt_scan\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "1.434 ns" { clk cnt_scan[0] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.09 % ) " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.903 ns" { clk cnt_scan[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt_scan[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.903 ns" { clk cnt_scan[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt_scan[13] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.903 ns" { clk cnt_scan[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt_scan[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.536 ns" { cnt_scan[0] cnt_scan[0]~173 cnt_scan[1]~169 cnt_scan[2]~165 cnt_scan[7]~145 cnt_scan[12]~125 cnt_scan[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.536 ns" { cnt_scan[0] cnt_scan[0]~173 cnt_scan[1]~169 cnt_scan[2]~165 cnt_scan[7]~145 cnt_scan[12]~125 cnt_scan[13] } { 0.000ns 0.533ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.903 ns" { clk cnt_scan[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt_scan[13] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.903 ns" { clk cnt_scan[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cnt_scan[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "" { cnt_scan[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { cnt_scan[13] } {  } {  } } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[1\] en_xhdl\[0\] 17.254 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[1\]\" through register \"en_xhdl\[0\]\" is 17.254 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.905 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "" { clk } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns cnt_scan\[15\] 2 REG LC_X7_Y8_N7 3 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X7_Y8_N7; Fanout = 3; REG Node = 'cnt_scan\[15\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "1.658 ns" { clk cnt_scan[15] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.067 ns) + CELL(0.711 ns) 7.905 ns en_xhdl\[0\] 3 REG LC_X27_Y20_N2 6 " "Info: 3: + IC(4.067 ns) + CELL(0.711 ns) = 7.905 ns; Loc. = LC_X27_Y20_N2; Fanout = 6; REG Node = 'en_xhdl\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "4.778 ns" { cnt_scan[15] en_xhdl[0] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.41 % ) " "Info: Total cell delay = 3.115 ns ( 39.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.790 ns ( 60.59 % ) " "Info: Total interconnect delay = 4.790 ns ( 60.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "7.905 ns" { clk cnt_scan[15] en_xhdl[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.905 ns" { clk clk~out0 cnt_scan[15] en_xhdl[0] } { 0.000ns 0.000ns 0.723ns 4.067ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.125 ns + Longest register pin " "Info: + Longest register to pin delay is 9.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en_xhdl\[0\] 1 REG LC_X27_Y20_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y20_N2; Fanout = 6; REG Node = 'en_xhdl\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "" { en_xhdl[0] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.698 ns) + CELL(0.292 ns) 2.990 ns data4\[0\]~164 2 COMB LC_X7_Y20_N7 7 " "Info: 2: + IC(2.698 ns) + CELL(0.292 ns) = 2.990 ns; Loc. = LC_X7_Y20_N7; Fanout = 7; COMB Node = 'data4\[0\]~164'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "2.990 ns" { en_xhdl[0] data4[0]~164 } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.590 ns) 4.052 ns Mux~112 3 COMB LC_X7_Y20_N6 1 " "Info: 3: + IC(0.472 ns) + CELL(0.590 ns) = 4.052 ns; Loc. = LC_X7_Y20_N6; Fanout = 1; COMB Node = 'Mux~112'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "1.062 ns" { data4[0]~164 Mux~112 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.965 ns) + CELL(2.108 ns) 9.125 ns dataout\[1\] 4 PIN PIN_197 0 " "Info: 4: + IC(2.965 ns) + CELL(2.108 ns) = 9.125 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'dataout\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "5.073 ns" { Mux~112 dataout[1] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.990 ns ( 32.77 % ) " "Info: Total cell delay = 2.990 ns ( 32.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.135 ns ( 67.23 % ) " "Info: Total interconnect delay = 6.135 ns ( 67.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "9.125 ns" { en_xhdl[0] data4[0]~164 Mux~112 dataout[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.125 ns" { en_xhdl[0] data4[0]~164 Mux~112 dataout[1] } { 0.000ns 2.698ns 0.472ns 2.965ns } { 0.000ns 0.292ns 0.590ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "7.905 ns" { clk cnt_scan[15] en_xhdl[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.905 ns" { clk clk~out0 cnt_scan[15] en_xhdl[0] } { 0.000ns 0.000ns 0.723ns 4.067ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "9.125 ns" { en_xhdl[0] data4[0]~164 Mux~112 dataout[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.125 ns" { en_xhdl[0] data4[0]~164 Mux~112 dataout[1] } { 0.000ns 2.698ns 0.472ns 2.965ns } { 0.000ns 0.292ns 0.590ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "datain\[0\] dataout\[1\] 13.857 ns Longest " "Info: Longest tpd from source pin \"datain\[0\]\" to destination pin \"dataout\[1\]\" is 13.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns datain\[0\] 1 PIN PIN_240 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 1; PIN Node = 'datain\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "" { datain[0] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.657 ns) + CELL(0.590 ns) 7.722 ns data4\[0\]~164 2 COMB LC_X7_Y20_N7 7 " "Info: 2: + IC(5.657 ns) + CELL(0.590 ns) = 7.722 ns; Loc. = LC_X7_Y20_N7; Fanout = 7; COMB Node = 'data4\[0\]~164'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "6.247 ns" { datain[0] data4[0]~164 } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.590 ns) 8.784 ns Mux~112 3 COMB LC_X7_Y20_N6 1 " "Info: 3: + IC(0.472 ns) + CELL(0.590 ns) = 8.784 ns; Loc. = LC_X7_Y20_N6; Fanout = 1; COMB Node = 'Mux~112'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "1.062 ns" { data4[0]~164 Mux~112 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.965 ns) + CELL(2.108 ns) 13.857 ns dataout\[1\] 4 PIN PIN_197 0 " "Info: 4: + IC(2.965 ns) + CELL(2.108 ns) = 13.857 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'dataout\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "5.073 ns" { Mux~112 dataout[1] } "NODE_NAME" } "" } } { "dial1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/dial1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.763 ns ( 34.37 % ) " "Info: Total cell delay = 4.763 ns ( 34.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.094 ns ( 65.63 % ) " "Info: Total interconnect delay = 9.094 ns ( 65.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DIAL1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/db/DIAL1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/接口实验/拨码开关/DIAL2/" "" "13.857 ns" { datain[0] data4[0]~164 Mux~112 dataout[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.857 ns" { datain[0] datain[0]~out0 data4[0]~164 Mux~112 dataout[1] } { 0.000ns 0.000ns 5.657ns 0.472ns 2.965ns } { 0.000ns 1.475ns 0.590ns 0.590ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}