lcd1.fit.qmsg

FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 03 11:13:16 2006 " "Info: Processing started: Fri Nov 03 11:13:16 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off lcd1 -c lcd1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcd1 -c lcd1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "lcd1 EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"lcd1\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 29" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "div_cnt\[14\] Global clock " "Info: Automatically promoted some destinations of signal \"div_cnt\[14\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "div_cnt\[14\] " "Info: Destination \"div_cnt\[14\]\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 53 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 53 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRST Global clock " "Info: Automatically promoted some destinations of signal \"nRST\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd_e~reg0 " "Info: Destination \"lcd_e~reg0\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[0\]~reg0 " "Info: Destination \"data\[0\]~reg0\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[1\]~reg0 " "Info: Destination \"data\[1\]~reg0\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[2\]~reg0 " "Info: Destination \"data\[2\]~reg0\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[3\]~reg0 " "Info: Destination \"data\[3\]~reg0\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[4\]~reg0 " "Info: Destination \"data\[4\]~reg0\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd_RSTB~123 " "Info: Destination \"lcd_RSTB~123\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 15 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[5\]~1044 " "Info: Destination \"data\[5\]~1044\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd_rs~612 " "Info: Destination \"lcd_rs~612\" may be non-global or may not use global clock" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 11 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 10 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nRST " "Info: Pin \"nRST\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "nRST" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "" { nRST } "NODE_NAME" } "" } } { "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.fld" "" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.fld" "" "" { nRST } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}