lcd1.tan.qmsg

来自「FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码」· QMSG 代码 · 共 11 行 · 第 1/4 页

{ "Info" "ITDB_TSU_RESULT" "lcd_rs~reg0 nRST clk 3.424 ns register " "Info: tsu for register \"lcd_rs~reg0\" (data pin = \"nRST\", clock pin = \"clk\") is 3.424 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.283 ns + Longest pin register " "Info: + Longest pin to register delay is 11.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns nRST 1 PIN PIN_67 37 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 37; PIN Node = 'nRST'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "" { nRST } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.168 ns) + CELL(0.292 ns) 9.935 ns lcd_rs~612 2 COMB LC_X14_Y15_N7 1 " "Info: 2: + IC(8.168 ns) + CELL(0.292 ns) = 9.935 ns; Loc. = LC_X14_Y15_N7; Fanout = 1; COMB Node = 'lcd_rs~612'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "8.460 ns" { nRST lcd_rs~612 } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.481 ns) + CELL(0.867 ns) 11.283 ns lcd_rs~reg0 3 REG LC_X14_Y15_N2 1 " "Info: 3: + IC(0.481 ns) + CELL(0.867 ns) = 11.283 ns; Loc. = LC_X14_Y15_N2; Fanout = 1; REG Node = 'lcd_rs~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "1.348 ns" { lcd_rs~612 lcd_rs~reg0 } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.634 ns ( 23.34 % ) " "Info: Total cell delay = 2.634 ns ( 23.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.649 ns ( 76.66 % ) " "Info: Total interconnect delay = 8.649 ns ( 76.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "11.283 ns" { nRST lcd_rs~612 lcd_rs~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.283 ns" { nRST nRST~out0 lcd_rs~612 lcd_rs~reg0 } { 0.000ns 0.000ns 8.168ns 0.481ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.896 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.896 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "" { clk } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns div_cnt\[14\] 2 REG LC_X7_Y8_N7 25 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X7_Y8_N7; Fanout = 25; REG Node = 'div_cnt\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "1.658 ns" { clk div_cnt[14] } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.058 ns) + CELL(0.711 ns) 7.896 ns lcd_rs~reg0 3 REG LC_X14_Y15_N2 1 " "Info: 3: + IC(4.058 ns) + CELL(0.711 ns) = 7.896 ns; Loc. = LC_X14_Y15_N2; Fanout = 1; REG Node = 'lcd_rs~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "4.769 ns" { div_cnt[14] lcd_rs~reg0 } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.45 % ) " "Info: Total cell delay = 3.115 ns ( 39.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.781 ns ( 60.55 % ) " "Info: Total interconnect delay = 4.781 ns ( 60.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "7.896 ns" { clk div_cnt[14] lcd_rs~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.896 ns" { clk clk~out0 div_cnt[14] lcd_rs~reg0 } { 0.000ns 0.000ns 0.723ns 4.058ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "11.283 ns" { nRST lcd_rs~612 lcd_rs~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.283 ns" { nRST nRST~out0 lcd_rs~612 lcd_rs~reg0 } { 0.000ns 0.000ns 8.168ns 0.481ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "7.896 ns" { clk div_cnt[14] lcd_rs~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.896 ns" { clk clk~out0 div_cnt[14] lcd_rs~reg0 } { 0.000ns 0.000ns 0.723ns 4.058ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lcd_RSTB lcd_RSTB~reg0 13.896 ns register " "Info: tco from clock \"clk\" to destination pin \"lcd_RSTB\" through register \"lcd_RSTB~reg0\" is 13.896 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.896 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.896 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "" { clk } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns div_cnt\[14\] 2 REG LC_X7_Y8_N7 25 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X7_Y8_N7; Fanout = 25; REG Node = 'div_cnt\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "1.658 ns" { clk div_cnt[14] } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.058 ns) + CELL(0.711 ns) 7.896 ns lcd_RSTB~reg0 3 REG LC_X14_Y14_N7 2 " "Info: 3: + IC(4.058 ns) + CELL(0.711 ns) = 7.896 ns; Loc. = LC_X14_Y14_N7; Fanout = 2; REG Node = 'lcd_RSTB~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "4.769 ns" { div_cnt[14] lcd_RSTB~reg0 } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.45 % ) " "Info: Total cell delay = 3.115 ns ( 39.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.781 ns ( 60.55 % ) " "Info: Total interconnect delay = 4.781 ns ( 60.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "7.896 ns" { clk div_cnt[14] lcd_RSTB~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.896 ns" { clk clk~out0 div_cnt[14] lcd_RSTB~reg0 } { 0.000ns 0.000ns 0.723ns 4.058ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.776 ns + Longest register pin " "Info: + Longest register to pin delay is 5.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd_RSTB~reg0 1 REG LC_X14_Y14_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y14_N7; Fanout = 2; REG Node = 'lcd_RSTB~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "" { lcd_RSTB~reg0 } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.668 ns) + CELL(2.108 ns) 5.776 ns lcd_RSTB 2 PIN PIN_184 0 " "Info: 2: + IC(3.668 ns) + CELL(2.108 ns) = 5.776 ns; Loc. = PIN_184; Fanout = 0; PIN Node = 'lcd_RSTB'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "5.776 ns" { lcd_RSTB~reg0 lcd_RSTB } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 36.50 % ) " "Info: Total cell delay = 2.108 ns ( 36.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.668 ns ( 63.50 % ) " "Info: Total interconnect delay = 3.668 ns ( 63.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "5.776 ns" { lcd_RSTB~reg0 lcd_RSTB } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.776 ns" { lcd_RSTB~reg0 lcd_RSTB } { 0.000ns 3.668ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "7.896 ns" { clk div_cnt[14] lcd_RSTB~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.896 ns" { clk clk~out0 div_cnt[14] lcd_RSTB~reg0 } { 0.000ns 0.000ns 0.723ns 4.058ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "5.776 ns" { lcd_RSTB~reg0 lcd_RSTB } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.776 ns" { lcd_RSTB~reg0 lcd_RSTB } { 0.000ns 3.668ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "data\[3\]~reg0 nRST clk -1.507 ns register " "Info: th for register \"data\[3\]~reg0\" (data pin = \"nRST\", clock pin = \"clk\") is -1.507 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.896 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.896 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "" { clk } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns div_cnt\[14\] 2 REG LC_X7_Y8_N7 25 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X7_Y8_N7; Fanout = 25; REG Node = 'div_cnt\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "1.658 ns" { clk div_cnt[14] } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.058 ns) + CELL(0.711 ns) 7.896 ns data\[3\]~reg0 3 REG LC_X13_Y14_N7 5 " "Info: 3: + IC(4.058 ns) + CELL(0.711 ns) = 7.896 ns; Loc. = LC_X13_Y14_N7; Fanout = 5; REG Node = 'data\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "4.769 ns" { div_cnt[14] data[3]~reg0 } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.45 % ) " "Info: Total cell delay = 3.115 ns ( 39.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.781 ns ( 60.55 % ) " "Info: Total interconnect delay = 4.781 ns ( 60.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "7.896 ns" { clk div_cnt[14] data[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.896 ns" { clk clk~out0 div_cnt[14] data[3]~reg0 } { 0.000ns 0.000ns 0.723ns 4.058ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.418 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.418 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns nRST 1 PIN PIN_67 37 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 37; PIN Node = 'nRST'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "" { nRST } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.336 ns) + CELL(0.607 ns) 9.418 ns data\[3\]~reg0 2 REG LC_X13_Y14_N7 5 " "Info: 2: + IC(7.336 ns) + CELL(0.607 ns) = 9.418 ns; Loc. = LC_X13_Y14_N7; Fanout = 5; REG Node = 'data\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "7.943 ns" { nRST data[3]~reg0 } "NODE_NAME" } "" } } { "lcd1.vhd" "" { Text "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/lcd1.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 22.11 % ) " "Info: Total cell delay = 2.082 ns ( 22.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.336 ns ( 77.89 % ) " "Info: Total interconnect delay = 7.336 ns ( 77.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "9.418 ns" { nRST data[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.418 ns" { nRST nRST~out0 data[3]~reg0 } { 0.000ns 0.000ns 7.336ns } { 0.000ns 1.475ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "7.896 ns" { clk div_cnt[14] data[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.896 ns" { clk clk~out0 div_cnt[14] data[3]~reg0 } { 0.000ns 0.000ns 0.723ns 4.058ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd1" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/db/lcd1.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-F/主板/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/vhdl/接口实验/12864液晶显示/lcd1/" "" "9.418 ns" { nRST data[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.418 ns" { nRST nRST~out0 data[3]~reg0 } { 0.000ns 0.000ns 7.336ns } { 0.000ns 1.475ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}