state_machine.vhd.bak

FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本的功能。如乘法器、加法器、多路选择器等。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY state_machine IS
   PORT (
      clk  : IN std_logic;   
      rst : IN std_logic;   
      c   : OUT std_logic_vector(7 DOWNTO 0);   
      en   : OUT std_logic_vector(7 DOWNTO 0));   
END state_machine;

ARCHITECTURE arch OF state_machine IS


   CONSTANT  state0   :  std_logic_vector(2 DOWNTO 0) := "000";    
   CONSTANT  state1    :  std_logic_vector(2 DOWNTO 0) := "001";    
   CONSTANT  state2  :  std_logic_vector(2 DOWNTO 0) := "010";    
   CONSTANT  state3  :  std_logic_vector(2 DOWNTO 0) := "011";    
   CONSTANT  state4 :  std_logic_vector(2 DOWNTO 0) := "100";    
   CONSTANT  state5 :  std_logic_vector(2 DOWNTO 0) := "101";    
   CONSTANT  state6   :  std_logic_vector(2 DOWNTO 0) := "110";    
   CONSTANT  state7   :  std_logic_vector(2 DOWNTO 0) := "111";    
   SIGNAL state    :  std_logic_vector(2 DOWNTO 0);   
   SIGNAL cnt       :  std_logic_vector(23 DOWNTO 0);    

BEGIN
   en <= "00000000" ;

   PROCESS
   BEGIN
      WAIT UNTIL (clk'EVENT AND clk = '1');
      IF (NOT rst = '1') THEN
         state <= state0;    
         cnt <= "000000000000000000000000";    
      ELSE
         cnt <= cnt + "000000000000000000000001";    
         IF (cnt = "111111111111111111111111") THEN
            CASE state IS
               WHEN state0 =>
                        state <= state1;    
               WHEN state1 =>
                        state <= state2;    
               WHEN state2 =>
                        state <= state3;    
               WHEN state3 =>
                        state <= state4;    
               WHEN state4 =>
                        state <= state5;    
               WHEN state5 =>
                        state <= state6;    
               WHEN state6 =>
                        state <= state7;    
               WHEN state7 =>
                        state <= state0;    
               WHEN OTHERS =>
                        NULL;
               
            END CASE;
         END IF;
      END IF;
   END PROCESS;

   PROCESS(state)
   BEGIN
      CASE state IS
         WHEN state0 =>
                  c <= "00000011";    
         WHEN state1 =>
                  c <= "10011111";    
         WHEN state2 =>
                  c <= "00100101";    
         WHEN state3 =>
                  c <= "00001101";    
         WHEN state4 =>
                  c <= "10011001";    
         WHEN state5 =>
                  c <= "01001001";    
         WHEN state6 =>
                  c <= "01000001";    
         WHEN state7 =>
                  c <= "00011111";    
         WHEN OTHERS =>
                  NULL;
         
      END CASE;
   END PROCESS;

END arch;