state_machine.tan.rpt

FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本的功能。如乘法器、加法器、多路选择器等。

; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[16]  ; cnt[23]  ; clk        ; clk      ; None                        ; None                      ; 2.348 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[14]  ; cnt[21]  ; clk        ; clk      ; None                        ; None                      ; 2.345 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[14]  ; cnt[20]  ; clk        ; clk      ; None                        ; None                      ; 2.345 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[14]  ; cnt[17]  ; clk        ; clk      ; None                        ; None                      ; 2.345 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[14]  ; cnt[18]  ; clk        ; clk      ; None                        ; None                      ; 2.345 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[14]  ; cnt[19]  ; clk        ; clk      ; None                        ; None                      ; 2.345 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[12]  ; cnt[17]  ; clk        ; clk      ; None                        ; None                      ; 2.338 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[12]  ; cnt[18]  ; clk        ; clk      ; None                        ; None                      ; 2.338 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;          ;          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+----------+------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To   ; From Clock ;
+-------+--------------+------------+----------+------+------------+
; N/A   ; None         ; 9.555 ns   ; state[0] ; c[7] ; clk        ;
; N/A   ; None         ; 9.545 ns   ; state[0] ; c[6] ; clk        ;
; N/A   ; None         ; 9.438 ns   ; state[2] ; c[7] ; clk        ;
; N/A   ; None         ; 9.419 ns   ; state[2] ; c[6] ; clk        ;
; N/A   ; None         ; 9.250 ns   ; state[1] ; c[7] ; clk        ;
; N/A   ; None         ; 9.247 ns   ; state[1] ; c[6] ; clk        ;
; N/A   ; None         ; 9.101 ns   ; state[0] ; c[5] ; clk        ;
; N/A   ; None         ; 9.096 ns   ; state[0] ; c[1] ; clk        ;
; N/A   ; None         ; 8.978 ns   ; state[2] ; c[5] ; clk        ;
; N/A   ; None         ; 8.967 ns   ; state[2] ; c[1] ; clk        ;
; N/A   ; None         ; 8.803 ns   ; state[1] ; c[5] ; clk        ;
; N/A   ; None         ; 8.799 ns   ; state[1] ; c[1] ; clk        ;
; N/A   ; None         ; 8.788 ns   ; state[0] ; c[3] ; clk        ;
; N/A   ; None         ; 8.785 ns   ; state[0] ; c[4] ; clk        ;
; N/A   ; None         ; 8.783 ns   ; state[0] ; c[2] ; clk        ;
; N/A   ; None         ; 8.670 ns   ; state[2] ; c[3] ; clk        ;
; N/A   ; None         ; 8.667 ns   ; state[2] ; c[4] ; clk        ;
; N/A   ; None         ; 8.665 ns   ; state[2] ; c[2] ; clk        ;
; N/A   ; None         ; 8.486 ns   ; state[1] ; c[2] ; clk        ;
; N/A   ; None         ; 8.484 ns   ; state[1] ; c[4] ; clk        ;
; N/A   ; None         ; 8.483 ns   ; state[1] ; c[3] ; clk        ;
+-------+--------------+------------+----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 20 15:51:56 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_machine -c state_machine --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 239.01 MHz between source register "cnt[2]" and destination register "state[2]" (period= 4.184 ns)
    Info: + Longest register to register delay is 3.903 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y13_N5; Fanout = 4; REG Node = 'cnt[2]'
        Info: 2: + IC(0.752 ns) + CELL(0.590 ns) = 1.342 ns; Loc. = LC_X23_Y13_N2; Fanout = 1; COMB Node = 'rtl~191'
        Info: 3: + IC(1.227 ns) + CELL(0.114 ns) = 2.683 ns; Loc. = LC_X24_Y12_N1; Fanout = 2; COMB Node = 'rtl~195'
        Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.979 ns; Loc. = LC_X24_Y12_N2; Fanout = 2; COMB Node = 'rtl~0'
        Info: 5: + IC(0.446 ns) + CELL(0.478 ns) = 3.903 ns; Loc. = LC_X24_Y12_N5; Fanout = 8; REG Node = 'state[2]'
        Info: Total cell delay = 1.296 ns ( 33.21 % )
        Info: Total interconnect delay = 2.607 ns ( 66.79 % )
    Info: - Smallest clock skew is -0.020 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X24_Y12_N5; Fanout = 8; REG Node = 'state[2]'
            Info: Total cell delay = 2.180 ns ( 74.10 % )
            Info: Total interconnect delay = 0.762 ns ( 25.90 % )
        Info: - Longest clock path from clock "clk" to source register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X23_Y13_N5; Fanout = 4; REG Node = 'cnt[2]'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "c[7]" through register "state[0]" is 9.555 ns
    Info: + Longest clock path from clock "clk" to source register is 2.942 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X24_Y12_N7; Fanout = 10; REG Node = 'state[0]'
        Info: Total cell delay = 2.180 ns ( 74.10 % )
        Info: Total interconnect delay = 0.762 ns ( 25.90 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.389 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y12_N7; Fanout = 10; REG Node = 'state[0]'
        Info: 2: + IC(1.825 ns) + CELL(0.442 ns) = 2.267 ns; Loc. = LC_X24_Y20_N4; Fanout = 1; COMB Node = 'Mux~292'
        Info: 3: + IC(2.014 ns) + CELL(2.108 ns) = 6.389 ns; Loc. = PIN_215; Fanout = 0; PIN Node = 'c[7]'
        Info: Total cell delay = 2.550 ns ( 39.91 % )
        Info: Total interconnect delay = 3.839 ns ( 60.09 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Oct 20 15:51:56 2006
    Info: Elapsed time: 00:00:00