sub.map.rpt

FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本的功能。如乘法器、加法器、多路选择器等。

+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                       ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                          ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------+
; sub.vhd                          ; yes             ; User VHDL File  ; E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/减法器/sub.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Total logic elements                        ; 11     ;
;     -- Combinational with no register       ; 11     ;
;     -- Register only                        ; 0      ;
;     -- Combinational with a register        ; 0      ;
;                                             ;        ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 7      ;
;     -- 3 input functions                    ; 3      ;
;     -- 2 input functions                    ; 1      ;
;     -- 1 input functions                    ; 0      ;
;     -- 0 input functions                    ; 0      ;
;         -- Combinational cells for routing  ; 0      ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 8      ;
;     -- arithmetic mode                      ; 3      ;
;     -- qfbk mode                            ; 0      ;
;     -- register cascade mode                ; 0      ;
;     -- synchronous clear/load mode          ; 0      ;
;     -- asynchronous clear/load mode         ; 0      ;
;                                             ;        ;
; Total registers                             ; 0      ;
; Total logic cells in carry chains           ; 4      ;
; I/O pins                                    ; 24     ;
; Maximum fan-out node                        ; add~26 ;
; Maximum fan-out                             ; 8      ;
; Total fan-out                               ; 46     ;
; Average fan-out                             ; 1.31   ;
+---------------------------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |sub                       ; 11 (11)     ; 0            ; 0           ; 24   ; 0            ; 11 (11)      ; 0 (0)             ; 0 (0)            ; 4 (4)           ; 0 (0)      ; |sub                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/减法器/sub.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 20 15:49:11 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sub -c sub
Info: Found 2 design units, including 1 entities, in source file sub.vhd
    Info: Found design unit 1: sub-arch
    Info: Found entity 1: sub
Info: Elaborating entity "sub" for the top level hierarchy
Info (10425): VHDL Case Statement information at sub.vhd(60): OTHERS choice is never selected
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "c[0]" stuck at VCC
    Warning: Pin "en[0]" stuck at GND
    Warning: Pin "en[1]" stuck at GND
    Warning: Pin "en[2]" stuck at GND
    Warning: Pin "en[3]" stuck at GND
    Warning: Pin "en[4]" stuck at GND
    Warning: Pin "en[5]" stuck at GND
    Warning: Pin "en[6]" stuck at GND
    Warning: Pin "en[7]" stuck at GND
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 16 output pins
    Info: Implemented 11 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Fri Oct 20 15:49:12 2006
    Info: Elapsed time: 00:00:01