mux.tan.qmsg

来自「FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本」· QMSG 代码 · 共 6 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 20 15:39:40 2006 " "Info: Processing started: Fri Oct 20 15:39:40 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a d\[1\] 15.904 ns Longest " "Info: Longest tpd from source pin \"a\" to destination pin \"d\[1\]\" is 15.904 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns a 1 PIN PIN_105 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_105; Fanout = 4; PIN Node = 'a'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/" "" "" { a } "NODE_NAME" } "" } } { "mux.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/mux.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.300 ns) + CELL(0.292 ns) 10.067 ns temp_xhd\[2\]~38 2 COMB LC_X14_Y20_N6 7 " "Info: 2: + IC(8.300 ns) + CELL(0.292 ns) = 10.067 ns; Loc. = LC_X14_Y20_N6; Fanout = 7; COMB Node = 'temp_xhd\[2\]~38'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/" "" "8.592 ns" { a temp_xhd[2]~38 } "NODE_NAME" } "" } } { "mux.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/mux.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.590 ns) 11.468 ns Mux~28 3 COMB LC_X15_Y20_N8 1 " "Info: 3: + IC(0.811 ns) + CELL(0.590 ns) = 11.468 ns; Loc. = LC_X15_Y20_N8; Fanout = 1; COMB Node = 'Mux~28'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/" "" "1.401 ns" { temp_xhd[2]~38 Mux~28 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.328 ns) + CELL(2.108 ns) 15.904 ns d\[1\] 4 PIN PIN_197 0 " "Info: 4: + IC(2.328 ns) + CELL(2.108 ns) = 15.904 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'd\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/" "" "4.436 ns" { Mux~28 d[1] } "NODE_NAME" } "" } } { "mux.vhd" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/mux.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.465 ns ( 28.07 % ) " "Info: Total cell delay = 4.465 ns ( 28.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.439 ns ( 71.93 % ) " "Info: Total interconnect delay = 11.439 ns ( 71.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/vhdl/基础实验/多路选择器/" "" "15.904 ns" { a temp_xhd[2]~38 Mux~28 d[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "15.904 ns" { a a~out0 temp_xhd[2]~38 Mux~28 d[1] } { 0.000ns 0.000ns 8.300ns 0.811ns 2.328ns } { 0.000ns 1.475ns 0.292ns 0.590ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 15:39:40 2006 " "Info: Processing ended: Fri Oct 20 15:39:40 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}