mux.fit.eqn
来自「FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本」· EQN 代码 · 共 244 行
EQN
244 行
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L37 is temp_xhd[0]~36 at LC_X14_Y20_N4
--operation mode is normal
A1L37 = a & b[0] # !a & (c[0]);
--A1L38 is temp_xhd[1]~37 at LC_X14_Y20_N5
--operation mode is normal
A1L38 = a & (b[1]) # !a & c[1];
--A1L39 is temp_xhd[2]~38 at LC_X14_Y20_N6
--operation mode is normal
A1L39 = a & (b[2]) # !a & c[2];
--A1L40 is temp_xhd[3]~39 at LC_X14_Y20_N2
--operation mode is normal
A1L40 = a & b[3] # !a & (c[3]);
--A1L30 is Mux~28 at LC_X15_Y20_N8
--operation mode is normal
A1L30 = A1L37 & (A1L40 # A1L39 $ A1L38) # !A1L37 & (A1L38 # A1L39 $ A1L40);
--A1L31 is Mux~29 at LC_X15_Y20_N4
--operation mode is normal
A1L31 = A1L39 & A1L37 & (A1L38 $ A1L40) # !A1L39 & !A1L40 & (A1L37 # A1L38);
--A1L32 is Mux~30 at LC_X15_Y20_N3
--operation mode is normal
A1L32 = A1L38 & (A1L37 & !A1L40) # !A1L38 & (A1L39 & (!A1L40) # !A1L39 & A1L37);
--A1L33 is Mux~31 at LC_X15_Y20_N9
--operation mode is normal
A1L33 = A1L37 & (A1L39 $ !A1L38) # !A1L37 & (A1L39 & !A1L38 & !A1L40 # !A1L39 & A1L38 & A1L40);
--A1L34 is Mux~32 at LC_X15_Y20_N5
--operation mode is normal
A1L34 = A1L39 & A1L40 & (A1L38 # !A1L37) # !A1L39 & !A1L37 & A1L38 & !A1L40;
--A1L35 is Mux~33 at LC_X15_Y20_N2
--operation mode is normal
A1L35 = A1L38 & (A1L37 & (A1L40) # !A1L37 & A1L39) # !A1L38 & A1L39 & (A1L37 $ A1L40);
--A1L36 is Mux~34 at LC_X14_Y20_N8
--operation mode is normal
A1L36 = A1L39 & !A1L38 & (A1L37 $ !A1L40) # !A1L39 & A1L37 & (A1L40 $ !A1L38);
--b[0] is b[0] at PIN_233
--operation mode is input
b[0] = INPUT();
--c[0] is c[0] at PIN_237
--operation mode is input
c[0] = INPUT();
--a is a at PIN_105
--operation mode is input
a = INPUT();
--b[1] is b[1] at PIN_234
--operation mode is input
b[1] = INPUT();
--c[1] is c[1] at PIN_238
--operation mode is input
c[1] = INPUT();
--b[2] is b[2] at PIN_235
--operation mode is input
b[2] = INPUT();
--c[2] is c[2] at PIN_239
--operation mode is input
c[2] = INPUT();
--b[3] is b[3] at PIN_236
--operation mode is input
b[3] = INPUT();
--c[3] is c[3] at PIN_240
--operation mode is input
c[3] = INPUT();
--d[0] is d[0] at PIN_194
--operation mode is output
d[0] = OUTPUT(VCC);
--d[1] is d[1] at PIN_197
--operation mode is output
d[1] = OUTPUT(!A1L30);
--d[2] is d[2] at PIN_200
--operation mode is output
d[2] = OUTPUT(A1L31);
--d[3] is d[3] at PIN_201
--operation mode is output
d[3] = OUTPUT(A1L32);
--d[4] is d[4] at PIN_202
--operation mode is output
d[4] = OUTPUT(A1L33);
--d[5] is d[5] at PIN_203
--operation mode is output
d[5] = OUTPUT(A1L34);
--d[6] is d[6] at PIN_214
--operation mode is output
d[6] = OUTPUT(A1L35);
--d[7] is d[7] at PIN_217
--operation mode is output
d[7] = OUTPUT(A1L36);
--en[0] is en[0] at PIN_193
--operation mode is output
en[0] = OUTPUT(GND);
--en[1] is en[1] at PIN_188
--operation mode is output
en[1] = OUTPUT(GND);
--en[2] is en[2] at PIN_187
--operation mode is output
en[2] = OUTPUT(GND);
--en[3] is en[3] at PIN_186
--operation mode is output
en[3] = OUTPUT(GND);
--en[4] is en[4] at PIN_185
--operation mode is output
en[4] = OUTPUT(GND);
--en[5] is en[5] at PIN_184
--operation mode is output
en[5] = OUTPUT(GND);
--en[6] is en[6] at PIN_183
--operation mode is output
en[6] = OUTPUT(GND);
--en[7] is en[7] at PIN_182
--operation mode is output
en[7] = OUTPUT(GND);
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