mux.tan.rpt
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RPT
162 行
Timing Analyzer report for mux
Fri Oct 20 15:39:40 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 15.904 ns ; a ; d[1] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 15.904 ns ; a ; d[1] ;
; N/A ; None ; 15.591 ns ; a ; d[3] ;
; N/A ; None ; 15.591 ns ; a ; d[2] ;
; N/A ; None ; 15.589 ns ; a ; d[4] ;
; N/A ; None ; 15.578 ns ; a ; d[5] ;
; N/A ; None ; 14.827 ns ; a ; d[6] ;
; N/A ; None ; 14.434 ns ; a ; d[7] ;
; N/A ; None ; 13.936 ns ; c[2] ; d[1] ;
; N/A ; None ; 13.723 ns ; b[2] ; d[1] ;
; N/A ; None ; 13.650 ns ; c[1] ; d[1] ;
; N/A ; None ; 13.623 ns ; c[2] ; d[3] ;
; N/A ; None ; 13.623 ns ; c[2] ; d[2] ;
; N/A ; None ; 13.621 ns ; c[2] ; d[4] ;
; N/A ; None ; 13.610 ns ; c[2] ; d[5] ;
; N/A ; None ; 13.604 ns ; c[0] ; d[1] ;
; N/A ; None ; 13.445 ns ; b[0] ; d[1] ;
; N/A ; None ; 13.410 ns ; b[2] ; d[3] ;
; N/A ; None ; 13.410 ns ; b[2] ; d[2] ;
; N/A ; None ; 13.408 ns ; b[2] ; d[4] ;
; N/A ; None ; 13.397 ns ; b[2] ; d[5] ;
; N/A ; None ; 13.345 ns ; b[3] ; d[1] ;
; N/A ; None ; 13.336 ns ; c[1] ; d[2] ;
; N/A ; None ; 13.335 ns ; c[1] ; d[4] ;
; N/A ; None ; 13.335 ns ; c[1] ; d[3] ;
; N/A ; None ; 13.317 ns ; c[1] ; d[5] ;
; N/A ; None ; 13.285 ns ; c[0] ; d[4] ;
; N/A ; None ; 13.283 ns ; c[0] ; d[2] ;
; N/A ; None ; 13.281 ns ; c[0] ; d[5] ;
; N/A ; None ; 13.278 ns ; c[0] ; d[3] ;
; N/A ; None ; 13.126 ns ; b[0] ; d[4] ;
; N/A ; None ; 13.124 ns ; b[0] ; d[2] ;
; N/A ; None ; 13.122 ns ; b[0] ; d[5] ;
; N/A ; None ; 13.119 ns ; b[0] ; d[3] ;
; N/A ; None ; 13.062 ns ; b[1] ; d[1] ;
; N/A ; None ; 13.026 ns ; b[3] ; d[4] ;
; N/A ; None ; 13.026 ns ; c[3] ; d[1] ;
; N/A ; None ; 13.024 ns ; b[3] ; d[2] ;
; N/A ; None ; 13.022 ns ; b[3] ; d[5] ;
; N/A ; None ; 13.019 ns ; b[3] ; d[3] ;
; N/A ; None ; 12.859 ns ; c[2] ; d[6] ;
; N/A ; None ; 12.748 ns ; b[1] ; d[2] ;
; N/A ; None ; 12.747 ns ; b[1] ; d[4] ;
; N/A ; None ; 12.747 ns ; b[1] ; d[3] ;
; N/A ; None ; 12.729 ns ; b[1] ; d[5] ;
; N/A ; None ; 12.707 ns ; c[3] ; d[4] ;
; N/A ; None ; 12.705 ns ; c[3] ; d[2] ;
; N/A ; None ; 12.703 ns ; c[3] ; d[5] ;
; N/A ; None ; 12.700 ns ; c[3] ; d[3] ;
; N/A ; None ; 12.646 ns ; b[2] ; d[6] ;
; N/A ; None ; 12.572 ns ; c[1] ; d[6] ;
; N/A ; None ; 12.515 ns ; c[0] ; d[6] ;
; N/A ; None ; 12.466 ns ; c[2] ; d[7] ;
; N/A ; None ; 12.356 ns ; b[0] ; d[6] ;
; N/A ; None ; 12.253 ns ; b[2] ; d[7] ;
; N/A ; None ; 12.252 ns ; b[3] ; d[6] ;
; N/A ; None ; 12.076 ns ; c[0] ; d[7] ;
; N/A ; None ; 11.984 ns ; b[1] ; d[6] ;
; N/A ; None ; 11.981 ns ; c[1] ; d[7] ;
; N/A ; None ; 11.960 ns ; b[3] ; d[7] ;
; N/A ; None ; 11.933 ns ; c[3] ; d[6] ;
; N/A ; None ; 11.917 ns ; b[0] ; d[7] ;
; N/A ; None ; 11.641 ns ; c[3] ; d[7] ;
; N/A ; None ; 11.393 ns ; b[1] ; d[7] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Oct 20 15:39:40 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux --timing_analysis_only
Info: Longest tpd from source pin "a" to destination pin "d[1]" is 15.904 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_105; Fanout = 4; PIN Node = 'a'
Info: 2: + IC(8.300 ns) + CELL(0.292 ns) = 10.067 ns; Loc. = LC_X14_Y20_N6; Fanout = 7; COMB Node = 'temp_xhd[2]~38'
Info: 3: + IC(0.811 ns) + CELL(0.590 ns) = 11.468 ns; Loc. = LC_X15_Y20_N8; Fanout = 1; COMB Node = 'Mux~28'
Info: 4: + IC(2.328 ns) + CELL(2.108 ns) = 15.904 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'd[1]'
Info: Total cell delay = 4.465 ns ( 28.07 % )
Info: Total interconnect delay = 11.439 ns ( 71.93 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Oct 20 15:39:40 2006
Info: Elapsed time: 00:00:01
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