📄 stm32f10x_dma.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 902] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\Obj\stm32f10x_dma.o --depend=..\Obj\stm32f10x_dma.d --device=DARMSTM -I..\..\..\..\..\INC\ST\STM32F10x -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_FLASH --omf_browse=..\Obj\stm32f10x_dma.crf ..\..\library\src\stm32f10x_dma.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
DMA_Cmd PROC
;;;236
;;;237 if (NewState != DISABLE)
000000 b121 CBZ r1,|L1.12|
;;;238 {
;;;239 /* Enable the selected DMA Channelx */
;;;240 DMA_Channelx->CCR |= CCR_ENABLE_Set;
000002 6802 LDR r2,[r0,#0]
000004 f042f042 ORR r2,r2,#1
000008 6002 STR r2,[r0,#0]
00000a e003 B |L1.20|
|L1.12|
;;;241 }
;;;242 else
;;;243 {
;;;244 /* Disable the selected DMA Channelx */
;;;245 DMA_Channelx->CCR &= CCR_ENABLE_Reset;
00000c 6802 LDR r2,[r0,#0]
00000e f022f022 BIC r2,r2,#1
000012 6002 STR r2,[r0,#0]
|L1.20|
;;;246 }
;;;247 }
000014 4770 BX lr
ENDP
DMA_DeInit PROC
;;;57 void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
;;;58 {
000016 b500 PUSH {lr}
000018 4603 MOV r3,r0
;;;59 /* DMA Channelx disable */
;;;60 DMA_Cmd(DMA_Channelx, DISABLE);
00001a 2100 MOVS r1,#0
00001c 4618 MOV r0,r3
00001e f7fff7ff BL DMA_Cmd
;;;61
;;;62 /* Reset Channelx control register */
;;;63 DMA_Channelx->CCR = 0;
000022 2000 MOVS r0,#0
000024 6018 STR r0,[r3,#0]
;;;64
;;;65 /* Reset Channelx remaining bytes register */
;;;66 DMA_Channelx->CNDTR = 0;
000026 6058 STR r0,[r3,#4]
;;;67
;;;68 /* Reset Channelx peripheral address register */
;;;69 DMA_Channelx->CPAR = 0;
000028 6098 STR r0,[r3,#8]
;;;70
;;;71 /* Reset Channelx memory address register */
;;;72 DMA_Channelx->CMAR = 0;
00002a 60d8 STR r0,[r3,#0xc]
;;;73
;;;74 switch (*(u32*)&DMA_Channelx)
00002c 4955 LDR r1,|L1.388|
00002e 1a58 SUBS r0,r3,r1
000030 428b CMP r3,r1
000032 d02a BEQ |L1.138|
000034 dc07 BGT |L1.70|
000036 4854 LDR r0,|L1.392|
000038 1818 ADDS r0,r3,r0
00003a d00b BEQ |L1.84|
00003c 2814 CMP r0,#0x14
00003e d012 BEQ |L1.102|
000040 2828 CMP r0,#0x28
000042 d146 BNE |L1.210|
000044 e018 B |L1.120|
|L1.70|
000046 2814 CMP r0,#0x14
000048 d028 BEQ |L1.156|
00004a 2828 CMP r0,#0x28
00004c d02f BEQ |L1.174|
00004e 283c CMP r0,#0x3c
000050 d13f BNE |L1.210|
000052 e035 B |L1.192|
|L1.84|
;;;75 {
;;;76 case DMA_Channel1_BASE:
;;;77 /* Reset interrupt pending bits for Channel1 */
;;;78 DMA->IFCR |= DMA_Channel1_IT_Mask;
000054 484b LDR r0,|L1.388|
000056 3844 SUBS r0,r0,#0x44
000058 6840 LDR r0,[r0,#4]
00005a f040f040 ORR r0,r0,#0xf
00005e 4949 LDR r1,|L1.388|
000060 3944 SUBS r1,r1,#0x44
000062 6048 STR r0,[r1,#4]
;;;79 break;
000064 e036 B |L1.212|
|L1.102|
;;;80
;;;81 case DMA_Channel2_BASE:
;;;82 /* Reset interrupt pending bits for Channel2 */
;;;83 DMA->IFCR |= DMA_Channel2_IT_Mask;
000066 4847 LDR r0,|L1.388|
000068 3844 SUBS r0,r0,#0x44
00006a 6840 LDR r0,[r0,#4]
00006c f040f040 ORR r0,r0,#0xf0
000070 4944 LDR r1,|L1.388|
000072 3944 SUBS r1,r1,#0x44
000074 6048 STR r0,[r1,#4]
;;;84 break;
000076 e02d B |L1.212|
|L1.120|
;;;85
;;;86 case DMA_Channel3_BASE:
;;;87 /* Reset interrupt pending bits for Channel3 */
;;;88 DMA->IFCR |= DMA_Channel3_IT_Mask;
000078 4842 LDR r0,|L1.388|
00007a 3844 SUBS r0,r0,#0x44
00007c 6840 LDR r0,[r0,#4]
00007e f440f440 ORR r0,r0,#0xf00
000082 4940 LDR r1,|L1.388|
000084 3944 SUBS r1,r1,#0x44
000086 6048 STR r0,[r1,#4]
;;;89 break;
000088 e024 B |L1.212|
|L1.138|
;;;90
;;;91 case DMA_Channel4_BASE:
;;;92 /* Reset interrupt pending bits for Channel4 */
;;;93 DMA->IFCR |= DMA_Channel4_IT_Mask;
00008a 483e LDR r0,|L1.388|
00008c 3844 SUBS r0,r0,#0x44
00008e 6840 LDR r0,[r0,#4]
000090 f440f440 ORR r0,r0,#0xf000
000094 493b LDR r1,|L1.388|
000096 3944 SUBS r1,r1,#0x44
000098 6048 STR r0,[r1,#4]
;;;94 break;
00009a e01b B |L1.212|
|L1.156|
;;;95
;;;96 case DMA_Channel5_BASE:
;;;97 /* Reset interrupt pending bits for Channel5 */
;;;98 DMA->IFCR |= DMA_Channel5_IT_Mask;
00009c 4839 LDR r0,|L1.388|
00009e 3844 SUBS r0,r0,#0x44
0000a0 6840 LDR r0,[r0,#4]
0000a2 f440f440 ORR r0,r0,#0xf0000
0000a6 4937 LDR r1,|L1.388|
0000a8 3944 SUBS r1,r1,#0x44
0000aa 6048 STR r0,[r1,#4]
;;;99 break;
0000ac e012 B |L1.212|
|L1.174|
;;;100
;;;101 case DMA_Channel6_BASE:
;;;102 /* Reset interrupt pending bits for Channel6 */
;;;103 DMA->IFCR |= DMA_Channel6_IT_Mask;
0000ae 4835 LDR r0,|L1.388|
0000b0 3844 SUBS r0,r0,#0x44
0000b2 6840 LDR r0,[r0,#4]
0000b4 f440f440 ORR r0,r0,#0xf00000
0000b8 4932 LDR r1,|L1.388|
0000ba 3944 SUBS r1,r1,#0x44
0000bc 6048 STR r0,[r1,#4]
;;;104 break;
0000be e009 B |L1.212|
|L1.192|
;;;105
;;;106 case DMA_Channel7_BASE:
;;;107 /* Reset interrupt pending bits for Channel7 */
;;;108 DMA->IFCR |= DMA_Channel7_IT_Mask;
0000c0 4830 LDR r0,|L1.388|
0000c2 3844 SUBS r0,r0,#0x44
0000c4 6840 LDR r0,[r0,#4]
0000c6 f040f040 ORR r0,r0,#0xf000000
0000ca 492e LDR r1,|L1.388|
0000cc 3944 SUBS r1,r1,#0x44
0000ce 6048 STR r0,[r1,#4]
;;;109 break;
0000d0 e000 B |L1.212|
|L1.210|
;;;110
;;;111 default:
;;;112 break;
0000d2 bf00 NOP
|L1.212|
0000d4 bf00 NOP
;;;113 }
;;;114 }
0000d6 bd00 POP {pc}
ENDP
DMA_Init PROC
;;;128 void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)
;;;129 {
0000d8 b510 PUSH {r4,lr}
;;;130 u32 tmpreg = 0;
0000da 2200 MOVS r2,#0
;;;131
;;;132 /* Check the parameters */
;;;133 assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
;;;134 assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
;;;135 assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
;;;136 assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
;;;137 assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;138 assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;139 assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;140 assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;141 assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
;;;142
;;;143 /*--------------------------- DMA Channelx CCR Configuration -----------------*/
;;;144 /* Get the DMA_Channelx CCR value */
;;;145 tmpreg = DMA_Channelx->CCR;
0000dc 6802 LDR r2,[r0,#0]
;;;146 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */
;;;147 tmpreg &= CCR_CLEAR_Mask;
0000de f647f647 MOV r3,#0x7ff0
0000e2 439a BICS r2,r2,r3
;;;148 /* Configure DMA Channelx: data transfer, data size, priority level and mode */
;;;149 /* Set DIR bit according to DMA_DIR value */
;;;150 /* Set CIRCULAR bit according to DMA_Mode value */
;;;151 /* Set PINC bit according to DMA_PeripheralInc value */
;;;152 /* Set MINC bit according to DMA_MemoryInc value */
;;;153 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;154 /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;155 /* Set PL bits according to DMA_Priority value */
;;;156 /* Set the MEM2MEM bit according to DMA_M2M value */
;;;157 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
0000e4 6a0c LDR r4,[r1,#0x20]
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