📄 stm32f10x_rcc.txt
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00024c 4355 MULS r5,r2,r5
00024e 6005 STR r5,[r0,#0]
|L1.592|
;;;717 }
;;;718 }
;;;719 break;
000250 e002 B |L1.600|
|L1.594|
;;;720
;;;721 default:
;;;722 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
000252 4d4c LDR r5,|L1.900|
000254 6005 STR r5,[r0,#0]
;;;723 break;
000256 bf00 NOP
|L1.600|
000258 bf00 NOP
;;;724 }
;;;725
;;;726 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;727 /* Get HCLK prescaler */
;;;728 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
00025a 4d45 LDR r5,|L1.880|
00025c 686d LDR r5,[r5,#4]
00025e f005f005 AND r1,r5,#0xf0
;;;729 tmp = tmp >> 4;
000262 0909 LSRS r1,r1,#4
;;;730 presc = APBAHBPrescTable[tmp];
000264 4d49 LDR r5,|L1.908|
000266 5c6c LDRB r4,[r5,r1]
;;;731
;;;732 /* HCLK clock frequency */
;;;733 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
000268 6805 LDR r5,[r0,#0]
00026a 40e5 LSRS r5,r5,r4
00026c 6045 STR r5,[r0,#4]
;;;734
;;;735 /* Get PCLK1 prescaler */
;;;736 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
00026e 4d40 LDR r5,|L1.880|
000270 686d LDR r5,[r5,#4]
000272 f405f405 AND r1,r5,#0x700
;;;737 tmp = tmp >> 8;
000276 0a09 LSRS r1,r1,#8
;;;738 presc = APBAHBPrescTable[tmp];
000278 4d44 LDR r5,|L1.908|
00027a 5c6c LDRB r4,[r5,r1]
;;;739
;;;740 /* PCLK1 clock frequency */
;;;741 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00027c 6845 LDR r5,[r0,#4]
00027e 40e5 LSRS r5,r5,r4
000280 6085 STR r5,[r0,#8]
;;;742
;;;743 /* Get PCLK2 prescaler */
;;;744 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
000282 4d3b LDR r5,|L1.880|
000284 686d LDR r5,[r5,#4]
000286 f405f405 AND r1,r5,#0x3800
;;;745 tmp = tmp >> 11;
00028a 0ac9 LSRS r1,r1,#11
;;;746 presc = APBAHBPrescTable[tmp];
00028c 4d3f LDR r5,|L1.908|
00028e 5c6c LDRB r4,[r5,r1]
;;;747
;;;748 /* PCLK2 clock frequency */
;;;749 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000290 6845 LDR r5,[r0,#4]
000292 40e5 LSRS r5,r5,r4
000294 60c5 STR r5,[r0,#0xc]
;;;750
;;;751 /* Get ADCCLK prescaler */
;;;752 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
000296 4d36 LDR r5,|L1.880|
000298 686d LDR r5,[r5,#4]
00029a f405f405 AND r1,r5,#0xc000
;;;753 tmp = tmp >> 14;
00029e 0b89 LSRS r1,r1,#14
;;;754 presc = ADCPrescTable[tmp];
0002a0 4d3a LDR r5,|L1.908|
0002a2 3510 ADDS r5,r5,#0x10
0002a4 5c6c LDRB r4,[r5,r1]
;;;755
;;;756 /* ADCCLK clock frequency */
;;;757 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
0002a6 68c5 LDR r5,[r0,#0xc]
0002a8 fbb5fbb5 UDIV r5,r5,r4
0002ac 6105 STR r5,[r0,#0x10]
;;;758 }
0002ae bd30 POP {r4,r5,pc}
ENDP
RCC_AHBPeriphClockCmd PROC
;;;779
;;;780 if (NewState != DISABLE)
0002b0 b129 CBZ r1,|L1.702|
;;;781 {
;;;782 RCC->AHBENR |= RCC_AHBPeriph;
0002b2 4a2f LDR r2,|L1.880|
0002b4 6952 LDR r2,[r2,#0x14]
0002b6 4302 ORRS r2,r2,r0
0002b8 4b2d LDR r3,|L1.880|
0002ba 615a STR r2,[r3,#0x14]
0002bc e004 B |L1.712|
|L1.702|
;;;783 }
;;;784 else
;;;785 {
;;;786 RCC->AHBENR &= ~RCC_AHBPeriph;
0002be 4a2c LDR r2,|L1.880|
0002c0 6952 LDR r2,[r2,#0x14]
0002c2 4382 BICS r2,r2,r0
0002c4 4b2a LDR r3,|L1.880|
0002c6 615a STR r2,[r3,#0x14]
|L1.712|
;;;787 }
;;;788 }
0002c8 4770 BX lr
ENDP
RCC_APB2PeriphClockCmd PROC
;;;810
;;;811 if (NewState != DISABLE)
0002ca b129 CBZ r1,|L1.728|
;;;812 {
;;;813 RCC->APB2ENR |= RCC_APB2Periph;
0002cc 4a28 LDR r2,|L1.880|
0002ce 6992 LDR r2,[r2,#0x18]
0002d0 4302 ORRS r2,r2,r0
0002d2 4b27 LDR r3,|L1.880|
0002d4 619a STR r2,[r3,#0x18]
0002d6 e004 B |L1.738|
|L1.728|
;;;814 }
;;;815 else
;;;816 {
;;;817 RCC->APB2ENR &= ~RCC_APB2Periph;
0002d8 4a25 LDR r2,|L1.880|
0002da 6992 LDR r2,[r2,#0x18]
0002dc 4382 BICS r2,r2,r0
0002de 4b24 LDR r3,|L1.880|
0002e0 619a STR r2,[r3,#0x18]
|L1.738|
;;;818 }
;;;819 }
0002e2 4770 BX lr
ENDP
RCC_APB1PeriphClockCmd PROC
;;;842
;;;843 if (NewState != DISABLE)
0002e4 b129 CBZ r1,|L1.754|
;;;844 {
;;;845 RCC->APB1ENR |= RCC_APB1Periph;
0002e6 4a22 LDR r2,|L1.880|
0002e8 69d2 LDR r2,[r2,#0x1c]
0002ea 4302 ORRS r2,r2,r0
0002ec 4b20 LDR r3,|L1.880|
0002ee 61da STR r2,[r3,#0x1c]
0002f0 e004 B |L1.764|
|L1.754|
;;;846 }
;;;847 else
;;;848 {
;;;849 RCC->APB1ENR &= ~RCC_APB1Periph;
0002f2 4a1f LDR r2,|L1.880|
0002f4 69d2 LDR r2,[r2,#0x1c]
0002f6 4382 BICS r2,r2,r0
0002f8 4b1d LDR r3,|L1.880|
0002fa 61da STR r2,[r3,#0x1c]
|L1.764|
;;;850 }
;;;851 }
0002fc 4770 BX lr
ENDP
RCC_APB2PeriphResetCmd PROC
;;;872
;;;873 if (NewState != DISABLE)
0002fe b129 CBZ r1,|L1.780|
;;;874 {
;;;875 RCC->APB2RSTR |= RCC_APB2Periph;
000300 4a1b LDR r2,|L1.880|
000302 68d2 LDR r2,[r2,#0xc]
000304 4302 ORRS r2,r2,r0
000306 4b1a LDR r3,|L1.880|
000308 60da STR r2,[r3,#0xc]
00030a e004 B |L1.790|
|L1.780|
;;;876 }
;;;877 else
;;;878 {
;;;879 RCC->APB2RSTR &= ~RCC_APB2Periph;
00030c 4a18 LDR r2,|L1.880|
00030e 68d2 LDR r2,[r2,#0xc]
000310 4382 BICS r2,r2,r0
000312 4b17 LDR r3,|L1.880|
000314 60da STR r2,[r3,#0xc]
|L1.790|
;;;880 }
;;;881 }
000316 4770 BX lr
ENDP
RCC_APB1PeriphResetCmd PROC
;;;903
;;;904 if (NewState != DISABLE)
000318 b129 CBZ r1,|L1.806|
;;;905 {
;;;906 RCC->APB1RSTR |= RCC_APB1Periph;
00031a 4a15 LDR r2,|L1.880|
00031c 6912 LDR r2,[r2,#0x10]
00031e 4302 ORRS r2,r2,r0
000320 4b13 LDR r3,|L1.880|
000322 611a STR r2,[r3,#0x10]
000324 e004 B |L1.816|
|L1.806|
;;;907 }
;;;908 else
;;;909 {
;;;910 RCC->APB1RSTR &= ~RCC_APB1Periph;
000326 4a12 LDR r2,|L1.880|
000328 6912 LDR r2,[r2,#0x10]
00032a 4382 BICS r2,r2,r0
00032c 4b10 LDR r3,|L1.880|
00032e 611a STR r2,[r3,#0x10]
|L1.816|
;;;911 }
;;;912 }
000330 4770 BX lr
ENDP
RCC_BackupResetCmd PROC
;;;926
;;;927 *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
000332 4913 LDR r1,|L1.896|
000334 3940 SUBS r1,r1,#0x40
000336 6008 STR r0,[r1,#0]
;;;928 }
000338 4770 BX lr
ENDP
RCC_ClockSecuritySystemCmd PROC
;;;942
;;;943 *(vu32 *) CR_CSSON_BB = (u32)NewState;
00033a 4910 LDR r1,|L1.892|
00033c 64c8 STR r0,[r1,#0x4c]
;;;944 }
00033e 4770 BX lr
ENDP
RCC_MCOConfig PROC
;;;964 /* Perform Byte access to MCO[26:24] bits to select the MCO source */
;;;965 *(vu8 *) 0x40021007 = RCC_MCO;
000340 490b LDR r1,|L1.880|
000342 71c8 STRB r0,[r1,#7]
;;;966 }
000344 4770 BX lr
ENDP
RCC_ClearFlag PROC
;;;1040 /* Set RMVF bit to clear the reset flags */
;;;1041 RCC->CSR |= CSR_RMVF_Set;
000346 480a LDR r0,|L1.880|
000348 6a40 LDR r0,[r0,#0x24]
00034a f040f040 ORR r0,r0,#0x1000000
00034e 4908 LDR r1,|L1.880|
000350 6248 STR r0,[r1,#0x24]
;;;1042 }
000352 4770 BX lr
ENDP
RCC_GetITStatus PROC
;;;1058 ITStatus RCC_GetITStatus(u8 RCC_IT)
;;;1059 {
000354 4601 MOV r1,r0
;;;1060 ITStatus bitstatus = RESET;
000356 2000 MOVS r0,#0
;;;1061
;;;1062 /* Check the parameters */
;;;1063 assert(IS_RCC_GET_IT(RCC_IT));
;;;1064
;;;1065 /* Check the status of the specified RCC interrupt */
;;;1066 if ((RCC->CIR & RCC_IT) != (u32)RESET)
000358 4a05 LDR r2,|L1.880|
00035a 6892 LDR r2,[r2,#8]
00035c 420a TST r2,r1
00035e d001 BEQ |L1.868|
;;;1067 {
;;;1068 bitstatus = SET;
000360 2001 MOVS r0,#1
000362 e000 B |L1.870|
|L1.868|
;;;1069 }
;;;1070 else
;;;1071 {
;;;1072 bitstatus = RESET;
000364 2000 MOVS r0,#0
|L1.870|
;;;1073 }
;;;1074
;;;1075 /* Return the RCC_IT status */
;;;1076 return bitstatus;
;;;1077 }
000366 4770 BX lr
ENDP
RCC_ClearITPendingBit PROC
;;;1099 pending bits */
;;;1100 *(vu8 *) 0x4002100A = RCC_IT;
000368 4901 LDR r1,|L1.880|
00036a 7288 STRB r0,[r1,#0xa]
;;;1101 }
00036c 4770 BX lr
ENDP
00036e 0000 DCW 0x0000
|L1.880|
000370 40021000 DCD 0x40021000
|L1.884|
000374 f8ff0000 DCD 0xf8ff0000
|L1.888|
000378 fef6ffff DCD 0xfef6ffff
|L1.892|
00037c 42420000 DCD 0x42420000
|L1.896|
000380 42420480 DCD 0x42420480
|L1.900|
000384 007a1200 DCD 0x007a1200
|L1.904|
000388 003d0900 DCD 0x003d0900
|L1.908|
00038c 00000000 DCD ||.constdata||
AREA ||.constdata||, DATA, READONLY, ALIGN=0
APBAHBPrescTable
000000 00000000 DCB 0x00,0x00,0x00,0x00
000004 01020304 DCB 0x01,0x02,0x03,0x04
000008 01020304 DCB 0x01,0x02,0x03,0x04
00000c 06070809 DCB 0x06,0x07,0x08,0x09
ADCPrescTable
000010 02040608 DCB 0x02,0x04,0x06,0x08
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