📄 stm32f10x_rcc.txt
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;;;355 tmpreg &= CFGR_SW_Mask;
00012a f021f021 BIC r1,r1,#3
;;;356
;;;357 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;358 tmpreg |= RCC_SYSCLKSource;
00012e 4301 ORRS r1,r1,r0
;;;359
;;;360 /* Store the new value */
;;;361 RCC->CFGR = tmpreg;
000130 6051 STR r1,[r2,#4]
;;;362 }
000132 4770 BX lr
ENDP
RCC_GetSYSCLKSource PROC
;;;376 {
;;;377 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
000134 488e LDR r0,|L1.880|
000136 6840 LDR r0,[r0,#4]
000138 f000f000 AND r0,r0,#0xc
;;;378 }
00013c 4770 BX lr
ENDP
RCC_HCLKConfig PROC
;;;399 {
;;;400 u32 tmpreg = 0;
00013e 2100 MOVS r1,#0
;;;401
;;;402 /* Check the parameters */
;;;403 assert(IS_RCC_HCLK(RCC_HCLK));
;;;404
;;;405 tmpreg = RCC->CFGR;
000140 4a8b LDR r2,|L1.880|
000142 6851 LDR r1,[r2,#4]
;;;406
;;;407 /* Clear HPRE[7:4] bits */
;;;408 tmpreg &= CFGR_HPRE_Reset_Mask;
000144 f021f021 BIC r1,r1,#0xf0
;;;409
;;;410 /* Set HPRE[7:4] bits according to RCC_HCLK value */
;;;411 tmpreg |= RCC_HCLK;
000148 4301 ORRS r1,r1,r0
;;;412
;;;413 /* Store the new value */
;;;414 RCC->CFGR = tmpreg;
00014a 6051 STR r1,[r2,#4]
;;;415 }
00014c 4770 BX lr
ENDP
RCC_PCLK1Config PROC
;;;432 {
;;;433 u32 tmpreg = 0;
00014e 2100 MOVS r1,#0
;;;434
;;;435 /* Check the parameters */
;;;436 assert(IS_RCC_PCLK(RCC_PCLK1));
;;;437
;;;438 tmpreg = RCC->CFGR;
000150 4a87 LDR r2,|L1.880|
000152 6851 LDR r1,[r2,#4]
;;;439
;;;440 /* Clear PPRE1[10:8] bits */
;;;441 tmpreg &= CFGR_PPRE1_Reset_Mask;
000154 f421f421 BIC r1,r1,#0x700
;;;442
;;;443 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
;;;444 tmpreg |= RCC_PCLK1;
000158 4301 ORRS r1,r1,r0
;;;445
;;;446 /* Store the new value */
;;;447 RCC->CFGR = tmpreg;
00015a 6051 STR r1,[r2,#4]
;;;448 }
00015c 4770 BX lr
ENDP
RCC_PCLK2Config PROC
;;;465 {
;;;466 u32 tmpreg = 0;
00015e 2100 MOVS r1,#0
;;;467
;;;468 /* Check the parameters */
;;;469 assert(IS_RCC_PCLK(RCC_PCLK2));
;;;470
;;;471 tmpreg = RCC->CFGR;
000160 4a83 LDR r2,|L1.880|
000162 6851 LDR r1,[r2,#4]
;;;472
;;;473 /* Clear PPRE2[13:11] bits */
;;;474 tmpreg &= CFGR_PPRE2_Reset_Mask;
000164 f421f421 BIC r1,r1,#0x3800
;;;475
;;;476 /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
;;;477 tmpreg |= RCC_PCLK2 << 3;
000168 ea41ea41 ORR r1,r1,r0,LSL #3
;;;478
;;;479 /* Store the new value */
;;;480 RCC->CFGR = tmpreg;
00016c 6051 STR r1,[r2,#4]
;;;481 }
00016e 4770 BX lr
ENDP
RCC_ITConfig PROC
;;;504
;;;505 if (NewState != DISABLE)
000170 b129 CBZ r1,|L1.382|
;;;506 {
;;;507 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
;;;508 *(vu8 *) 0x40021009 |= RCC_IT;
000172 4a7f LDR r2,|L1.880|
000174 7a52 LDRB r2,[r2,#9]
000176 4302 ORRS r2,r2,r0
000178 4b7d LDR r3,|L1.880|
00017a 725a STRB r2,[r3,#9]
00017c e004 B |L1.392|
|L1.382|
;;;509 }
;;;510 else
;;;511 {
;;;512 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
;;;513 *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
00017e 4a7c LDR r2,|L1.880|
000180 7a52 LDRB r2,[r2,#9]
000182 4382 BICS r2,r2,r0
000184 4b7a LDR r3,|L1.880|
000186 725a STRB r2,[r3,#9]
|L1.392|
;;;514 }
;;;515 }
000188 4770 BX lr
ENDP
RCC_USBCLKConfig PROC
;;;534
;;;535 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
00018a 497c LDR r1,|L1.892|
00018c 31d8 ADDS r1,r1,#0xd8
00018e 6008 STR r0,[r1,#0]
;;;536 }
000190 4770 BX lr
ENDP
RCC_ADCCLKConfig PROC
;;;552 {
;;;553 u32 tmpreg = 0;
000192 2100 MOVS r1,#0
;;;554
;;;555 /* Check the parameters */
;;;556 assert(IS_RCC_ADCCLK(RCC_ADCCLK));
;;;557
;;;558 tmpreg = RCC->CFGR;
000194 4a76 LDR r2,|L1.880|
000196 6851 LDR r1,[r2,#4]
;;;559
;;;560 /* Clear ADCPRE[15:14] bits */
;;;561 tmpreg &= CFGR_ADCPRE_Reset_Mask;
000198 f421f421 BIC r1,r1,#0xc000
;;;562
;;;563 /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
;;;564 tmpreg |= RCC_ADCCLK;
00019c 4301 ORRS r1,r1,r0
;;;565
;;;566 /* Store the new value */
;;;567 RCC->CFGR = tmpreg;
00019e 6051 STR r1,[r2,#4]
;;;568 }
0001a0 4770 BX lr
ENDP
RCC_LSEConfig PROC
;;;588 /* Reset LSEON bit */
;;;589 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
0001a2 2100 MOVS r1,#0
0001a4 4a72 LDR r2,|L1.880|
0001a6 3220 ADDS r2,r2,#0x20
0001a8 7011 STRB r1,[r2,#0]
;;;590
;;;591 /* Reset LSEBYP bit */
;;;592 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
0001aa 4a71 LDR r2,|L1.880|
0001ac f882f882 STRB r1,[r2,#0x20]
;;;593
;;;594 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;595 switch(RCC_LSE)
0001b0 2801 CMP r0,#1
0001b2 d002 BEQ |L1.442|
0001b4 2804 CMP r0,#4
0001b6 d10a BNE |L1.462|
0001b8 e004 B |L1.452|
|L1.442|
;;;596 {
;;;597 case RCC_LSE_ON:
;;;598 /* Set LSEON bit */
;;;599 *(vu8 *) BDCR_BASE = RCC_LSE_ON;
0001ba 2101 MOVS r1,#1
0001bc 4a6c LDR r2,|L1.880|
0001be 3220 ADDS r2,r2,#0x20
0001c0 7011 STRB r1,[r2,#0]
;;;600 break;
0001c2 e005 B |L1.464|
|L1.452|
;;;601
;;;602 case RCC_LSE_Bypass:
;;;603 /* Set LSEBYP and LSEON bits */
;;;604 *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
0001c4 2105 MOVS r1,#5
0001c6 4a6a LDR r2,|L1.880|
0001c8 3220 ADDS r2,r2,#0x20
0001ca 7011 STRB r1,[r2,#0]
;;;605 break;
0001cc e000 B |L1.464|
|L1.462|
;;;606
;;;607 default:
;;;608 break;
0001ce bf00 NOP
|L1.464|
0001d0 bf00 NOP
;;;609 }
;;;610 }
0001d2 4770 BX lr
ENDP
RCC_LSICmd PROC
;;;625
;;;626 *(vu32 *) CSR_LSION_BB = (u32)NewState;
0001d4 496a LDR r1,|L1.896|
0001d6 6008 STR r0,[r1,#0]
;;;627 }
0001d8 4770 BX lr
ENDP
RCC_RTCCLKConfig PROC
;;;648 /* Select the RTC clock source */
;;;649 RCC->BDCR |= RCC_RTCCLKSource;
0001da 4965 LDR r1,|L1.880|
0001dc 6a09 LDR r1,[r1,#0x20]
0001de 4301 ORRS r1,r1,r0
0001e0 4a63 LDR r2,|L1.880|
0001e2 6211 STR r1,[r2,#0x20]
;;;650 }
0001e4 4770 BX lr
ENDP
RCC_RTCCLKCmd PROC
;;;666
;;;667 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
0001e6 4966 LDR r1,|L1.896|
0001e8 3944 SUBS r1,r1,#0x44
0001ea 6008 STR r0,[r1,#0]
;;;668 }
0001ec 4770 BX lr
ENDP
RCC_GetClocksFreq PROC
;;;678 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
;;;679 {
0001ee b530 PUSH {r4,r5,lr}
;;;680 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
0001f0 2100 MOVS r1,#0
0001f2 2200 MOVS r2,#0
0001f4 2300 MOVS r3,#0
0001f6 2400 MOVS r4,#0
;;;681
;;;682 /* Get SYSCLK source -------------------------------------------------------*/
;;;683 tmp = RCC->CFGR & CFGR_SWS_Mask;
0001f8 4d5d LDR r5,|L1.880|
0001fa 686d LDR r5,[r5,#4]
0001fc f005f005 AND r1,r5,#0xc
;;;684
;;;685 switch (tmp)
000200 b121 CBZ r1,|L1.524|
000202 2904 CMP r1,#4
000204 d005 BEQ |L1.530|
000206 2908 CMP r1,#8
000208 d123 BNE |L1.594|
00020a e005 B |L1.536|
|L1.524|
;;;686 {
;;;687 case 0x00: /* HSI used as system clock */
;;;688 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
00020c 4d5d LDR r5,|L1.900|
00020e 6005 STR r5,[r0,#0]
;;;689 break;
000210 e022 B |L1.600|
|L1.530|
;;;690
;;;691 case 0x04: /* HSE used as system clock */
;;;692 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
000212 4d5c LDR r5,|L1.900|
000214 6005 STR r5,[r0,#0]
;;;693 break;
000216 e01f B |L1.600|
|L1.536|
;;;694
;;;695 case 0x08: /* PLL used as system clock */
;;;696 /* Get PLL clock source and multiplication factor ----------------------*/
;;;697 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
000218 4d55 LDR r5,|L1.880|
00021a 686d LDR r5,[r5,#4]
00021c f405f405 AND r2,r5,#0x3c0000
;;;698 pllmull = ( pllmull >> 18) + 2;
000220 2502 MOVS r5,#2
000222 eb05eb05 ADD r2,r5,r2,LSR #18
;;;699
;;;700 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
000226 4d52 LDR r5,|L1.880|
000228 686d LDR r5,[r5,#4]
00022a f405f405 AND r3,r5,#0x10000
;;;701
;;;702 if (pllsource == 0x00)
00022e b91b CBNZ r3,|L1.568|
;;;703 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;704 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
000230 4d55 LDR r5,|L1.904|
000232 4355 MULS r5,r2,r5
000234 6005 STR r5,[r0,#0]
000236 e00b B |L1.592|
|L1.568|
;;;705 }
;;;706 else
;;;707 {/* HSE selected as PLL clock entry */
;;;708
;;;709 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
000238 4d4d LDR r5,|L1.880|
00023a 686d LDR r5,[r5,#4]
00023c f415f415 TST r5,#0x20000
000240 d003 BEQ |L1.586|
;;;710 {/* HSE oscillator clock divided by 2 */
;;;711
;;;712 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
000242 4d51 LDR r5,|L1.904|
000244 4355 MULS r5,r2,r5
000246 6005 STR r5,[r0,#0]
000248 e002 B |L1.592|
|L1.586|
;;;713 }
;;;714 else
;;;715 {
;;;716 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
00024a 4d4e LDR r5,|L1.900|
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