📄 stm32f10x_rcc.txt
字号:
; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 902] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\Obj\stm32f10x_rcc.o --depend=..\Obj\stm32f10x_rcc.d --device=DARMSTM -I..\..\..\..\..\INC\ST\STM32F10x -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_FLASH --omf_browse=..\Obj\stm32f10x_rcc.crf ..\..\library\src\stm32f10x_rcc.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;126 /* Disable APB2 Peripheral Reset */
;;;127 RCC->APB2RSTR = 0x00000000;
000000 2000 MOVS r0,#0
000002 49db LDR r1,|L1.880|
000004 60c8 STR r0,[r1,#0xc]
;;;128
;;;129 /* Disable APB1 Peripheral Reset */
;;;130 RCC->APB1RSTR = 0x00000000;
000006 6108 STR r0,[r1,#0x10]
;;;131
;;;132 /* FLITF and SRAM Clock ON */
;;;133 RCC->AHBENR = 0x00000014;
000008 2014 MOVS r0,#0x14
00000a 6148 STR r0,[r1,#0x14]
;;;134
;;;135 /* Disable APB2 Peripheral Clock */
;;;136 RCC->APB2ENR = 0x00000000;
00000c 2000 MOVS r0,#0
00000e 6188 STR r0,[r1,#0x18]
;;;137
;;;138 /* Disable APB1 Peripheral Clock */
;;;139 RCC->APB1ENR = 0x00000000;
000010 61c8 STR r0,[r1,#0x1c]
;;;140
;;;141 /* Set HSION bit */
;;;142 RCC->CR |= (u32)0x00000001;
000012 4608 MOV r0,r1
000014 6800 LDR r0,[r0,#0]
000016 f040f040 ORR r0,r0,#1
00001a 6008 STR r0,[r1,#0]
;;;143
;;;144 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
;;;145 RCC->CFGR &= 0xF8FF0000;
00001c 4608 MOV r0,r1
00001e 6840 LDR r0,[r0,#4]
000020 49d4 LDR r1,|L1.884|
000022 4008 ANDS r0,r0,r1
000024 49d2 LDR r1,|L1.880|
000026 6048 STR r0,[r1,#4]
;;;146
;;;147 /* Reset HSEON, CSSON and PLLON bits */
;;;148 RCC->CR &= 0xFEF6FFFF;
000028 4608 MOV r0,r1
00002a 6800 LDR r0,[r0,#0]
00002c 49d2 LDR r1,|L1.888|
00002e 4008 ANDS r0,r0,r1
000030 49cf LDR r1,|L1.880|
000032 6008 STR r0,[r1,#0]
;;;149
;;;150 /* Reset HSEBYP bit */
;;;151 RCC->CR &= 0xFFFBFFFF;
000034 4608 MOV r0,r1
000036 6800 LDR r0,[r0,#0]
000038 f420f420 BIC r0,r0,#0x40000
00003c 6008 STR r0,[r1,#0]
;;;152
;;;153 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;154 RCC->CFGR &= 0xFF80FFFF;
00003e 4608 MOV r0,r1
000040 6840 LDR r0,[r0,#4]
000042 f420f420 BIC r0,r0,#0x7f0000
000046 6048 STR r0,[r1,#4]
;;;155
;;;156 /* Disable all interrupts */
;;;157 RCC->CIR = 0x00000000;
000048 2000 MOVS r0,#0
00004a 6088 STR r0,[r1,#8]
;;;158 }
00004c 4770 BX lr
ENDP
RCC_HSEConfig PROC
;;;180 /* Reset HSEON bit */
;;;181 RCC->CR &= CR_HSEON_Reset;
00004e 49c8 LDR r1,|L1.880|
000050 6809 LDR r1,[r1,#0]
000052 f421f421 BIC r1,r1,#0x10000
000056 4ac6 LDR r2,|L1.880|
000058 6011 STR r1,[r2,#0]
;;;182
;;;183 /* Reset HSEBYP bit */
;;;184 RCC->CR &= CR_HSEBYP_Reset;
00005a 4611 MOV r1,r2
00005c 6809 LDR r1,[r1,#0]
00005e f421f421 BIC r1,r1,#0x40000
000062 6011 STR r1,[r2,#0]
;;;185
;;;186 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;187 switch(RCC_HSE)
000064 f5b0f5b0 CMP r0,#0x10000
000068 d003 BEQ |L1.114|
00006a f5b0f5b0 CMP r0,#0x40000
00006e d10e BNE |L1.142|
000070 e006 B |L1.128|
|L1.114|
;;;188 {
;;;189 case RCC_HSE_ON:
;;;190 /* Set HSEON bit */
;;;191 RCC->CR |= CR_HSEON_Set;
000072 49bf LDR r1,|L1.880|
000074 6809 LDR r1,[r1,#0]
000076 f441f441 ORR r1,r1,#0x10000
00007a 4abd LDR r2,|L1.880|
00007c 6011 STR r1,[r2,#0]
;;;192 break;
00007e e007 B |L1.144|
|L1.128|
;;;193
;;;194 case RCC_HSE_Bypass:
;;;195 /* Set HSEBYP and HSEON bits */
;;;196 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
000080 49bb LDR r1,|L1.880|
000082 6809 LDR r1,[r1,#0]
000084 f441f441 ORR r1,r1,#0x50000
000088 4ab9 LDR r2,|L1.880|
00008a 6011 STR r1,[r2,#0]
;;;197 break;
00008c e000 B |L1.144|
|L1.142|
;;;198
;;;199 default:
;;;200 break;
00008e bf00 NOP
|L1.144|
000090 bf00 NOP
;;;201 }
;;;202 }
000092 4770 BX lr
ENDP
RCC_GetFlagStatus PROC
;;;987 FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
;;;988 {
000094 b510 PUSH {r4,lr}
000096 4601 MOV r1,r0
;;;989 u32 tmp = 0;
000098 2200 MOVS r2,#0
;;;990 u32 statusreg = 0;
00009a 2300 MOVS r3,#0
;;;991 FlagStatus bitstatus = RESET;
00009c 2000 MOVS r0,#0
;;;992
;;;993 /* Check the parameters */
;;;994 assert(IS_RCC_FLAG(RCC_FLAG));
;;;995
;;;996 /* Get the RCC register index */
;;;997 tmp = RCC_FLAG >> 5;
00009e 114a ASRS r2,r1,#5
;;;998
;;;999 if (tmp == 1) /* The flag to check is in CR register */
0000a0 2a01 CMP r2,#1
0000a2 d102 BNE |L1.170|
;;;1000 {
;;;1001 statusreg = RCC->CR;
0000a4 4cb2 LDR r4,|L1.880|
0000a6 6823 LDR r3,[r4,#0]
0000a8 e006 B |L1.184|
|L1.170|
;;;1002 }
;;;1003 else if (tmp == 2) /* The flag to check is in BDCR register */
0000aa 2a02 CMP r2,#2
0000ac d102 BNE |L1.180|
;;;1004 {
;;;1005 statusreg = RCC->BDCR;
0000ae 4cb0 LDR r4,|L1.880|
0000b0 6a23 LDR r3,[r4,#0x20]
0000b2 e001 B |L1.184|
|L1.180|
;;;1006 }
;;;1007 else /* The flag to check is in CSR register */
;;;1008 {
;;;1009 statusreg = RCC->CSR;
0000b4 4cae LDR r4,|L1.880|
0000b6 6a63 LDR r3,[r4,#0x24]
|L1.184|
;;;1010 }
;;;1011
;;;1012 /* Get the flag position */
;;;1013 tmp = RCC_FLAG & FLAG_Mask;
0000b8 f001f001 AND r2,r1,#0x1f
;;;1014
;;;1015 if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
0000bc 2401 MOVS r4,#1
0000be 4094 LSLS r4,r4,r2
0000c0 421c TST r4,r3
0000c2 d001 BEQ |L1.200|
;;;1016 {
;;;1017 bitstatus = SET;
0000c4 2001 MOVS r0,#1
0000c6 e000 B |L1.202|
|L1.200|
;;;1018 }
;;;1019 else
;;;1020 {
;;;1021 bitstatus = RESET;
0000c8 2000 MOVS r0,#0
|L1.202|
;;;1022 }
;;;1023
;;;1024 /* Return the flag status */
;;;1025 return bitstatus;
;;;1026 }
0000ca bd10 POP {r4,pc}
ENDP
RCC_WaitForHSEStartUp PROC
;;;213 ErrorStatus RCC_WaitForHSEStartUp(void)
;;;214 {
0000cc b510 PUSH {r4,lr}
;;;215 vu32 StartUpCounter = 0;
0000ce 2400 MOVS r4,#0
;;;216
;;;217 /* Wait till HSE is ready and if Time out is reached exit */
;;;218 while((RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET) &&
0000d0 e000 B |L1.212|
|L1.210|
;;;219 (StartUpCounter != HSEStartUp_TimeOut))
;;;220 {
;;;221 StartUpCounter++;
0000d2 1c64 ADDS r4,r4,#1
|L1.212|
0000d4 2031 MOVS r0,#0x31
0000d6 f7fff7ff BL RCC_GetFlagStatus
0000da b908 CBNZ r0,|L1.224|
0000dc 2c80 CMP r4,#0x80
0000de d1f8 BNE |L1.210|
|L1.224|
;;;222 }
;;;223
;;;224 if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
0000e0 2031 MOVS r0,#0x31
0000e2 f7fff7ff BL RCC_GetFlagStatus
0000e6 b108 CBZ r0,|L1.236|
;;;225 {
;;;226 return SUCCESS;
0000e8 2001 MOVS r0,#1
|L1.234|
;;;227 }
;;;228 else
;;;229 {
;;;230 return ERROR;
;;;231 }
;;;232 }
0000ea bd10 POP {r4,pc}
|L1.236|
0000ec 2000 MOVS r0,#0
0000ee e7fc B |L1.234|
ENDP
RCC_AdjustHSICalibrationValue PROC
;;;244 {
;;;245 u32 tmpreg = 0;
0000f0 2100 MOVS r1,#0
;;;246
;;;247 /* Check the parameters */
;;;248 assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
;;;249
;;;250 tmpreg = RCC->CR;
0000f2 4a9f LDR r2,|L1.880|
0000f4 6811 LDR r1,[r2,#0]
;;;251
;;;252 /* Clear HSITRIM[7:3] bits */
;;;253 tmpreg &= CR_HSITRIM_Mask;
0000f6 f021f021 BIC r1,r1,#0xf8
;;;254
;;;255 /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
;;;256 tmpreg |= (u32)HSICalibrationValue << 3;
0000fa ea41ea41 ORR r1,r1,r0,LSL #3
;;;257
;;;258 /* Store the new value */
;;;259 RCC->CR = tmpreg;
0000fe 6011 STR r1,[r2,#0]
;;;260 }
000100 4770 BX lr
ENDP
RCC_HSICmd PROC
;;;276
;;;277 *(vu32 *) CR_HSION_BB = (u32)NewState;
000102 499e LDR r1,|L1.892|
000104 6008 STR r0,[r1,#0]
;;;278 }
000106 4770 BX lr
ENDP
RCC_PLLConfig PROC
;;;298 {
;;;299 u32 tmpreg = 0;
000108 2200 MOVS r2,#0
;;;300
;;;301 /* Check the parameters */
;;;302 assert(IS_RCC_PLL_SOURCE(RCC_PLLSource));
;;;303 assert(IS_RCC_PLL_MUL(RCC_PLLMul));
;;;304
;;;305 tmpreg = RCC->CFGR;
00010a 4b99 LDR r3,|L1.880|
00010c 685a LDR r2,[r3,#4]
;;;306
;;;307 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
;;;308 tmpreg &= CFGR_PLL_Mask;
00010e f422f422 BIC r2,r2,#0x3f0000
;;;309
;;;310 /* Set the PLL configuration bits */
;;;311 tmpreg |= RCC_PLLSource | RCC_PLLMul;
000112 ea40ea40 ORR r3,r0,r1
000116 431a ORRS r2,r2,r3
;;;312
;;;313 /* Store the new value */
;;;314 RCC->CFGR = tmpreg;
000118 4b95 LDR r3,|L1.880|
00011a 605a STR r2,[r3,#4]
;;;315 }
00011c 4770 BX lr
ENDP
RCC_PLLCmd PROC
;;;330
;;;331 *(vu32 *) CR_PLLON_BB = (u32)NewState;
00011e 4997 LDR r1,|L1.892|
000120 6608 STR r0,[r1,#0x60]
;;;332 }
000122 4770 BX lr
ENDP
RCC_SYSCLKConfig PROC
;;;346 {
;;;347 u32 tmpreg = 0;
000124 2100 MOVS r1,#0
;;;348
;;;349 /* Check the parameters */
;;;350 assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
;;;351
;;;352 tmpreg = RCC->CFGR;
000126 4a92 LDR r2,|L1.880|
000128 6851 LDR r1,[r2,#4]
;;;353
;;;354 /* Clear SW[1:0] bits */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -