📄 stm32f10x_adc.txt
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;;;977 tmpreg2 = (u32)JSQR_JSQ_Set << (5 * ((Rank + 3) - (tmpreg3 + 1)));
000312 1cd7 ADDS r7,r2,#3
000314 f105f105 ADD r12,r5,#1
000318 eba7eba7 SUB r7,r7,r12
00031c eb07eb07 ADD r12,r7,r7,LSL #2
000320 271f MOVS r7,#0x1f
000322 fa07fa07 LSL r6,r7,r12
;;;978 /* Clear the old JSQx bits for the selected rank */
;;;979 tmpreg1 &= ~tmpreg2;
000326 43b4 BICS r4,r4,r6
;;;980 /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
;;;981 tmpreg2 = (u32)ADC_Channel << (5 * ((Rank + 3) - (tmpreg3 + 1)));
000328 1cd7 ADDS r7,r2,#3
00032a f105f105 ADD r12,r5,#1
00032e eba7eba7 SUB r7,r7,r12
000332 eb07eb07 ADD r7,r7,r7,LSL #2
000336 fa01fa01 LSL r6,r1,r7
;;;982 /* Set the JSQx bits for the selected rank */
;;;983 tmpreg1 |= tmpreg2;
00033a 4334 ORRS r4,r4,r6
;;;984 /* Store the new register value */
;;;985 ADCx->JSQR = tmpreg1;
00033c 6384 STR r4,[r0,#0x38]
;;;986 }
00033e bdf0 POP {r4-r7,pc}
ENDP
ADC_InjectedSequencerLengthConfig PROC
;;;997 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length)
;;;998 {
000340 b510 PUSH {r4,lr}
;;;999 u32 tmpreg1 = 0;
000342 2200 MOVS r2,#0
;;;1000 u8 tmpreg2 = 0;
000344 2300 MOVS r3,#0
;;;1001
;;;1002 /* Check the parameters */
;;;1003 assert(IS_ADC_INJECTED_LENGTH(Length));
;;;1004
;;;1005 /* Get the old register value */
;;;1006 tmpreg1 = ADCx->JSQR;
000346 6b82 LDR r2,[r0,#0x38]
;;;1007 /* Clear the old injected sequnence lenght JL bits */
;;;1008 tmpreg1 &= JSQR_JL_Reset;
000348 f422f422 BIC r2,r2,#0x300000
;;;1009 /* Set the injected sequnence lenght JL bits */
;;;1010 tmpreg2 = Length - 1;
00034c 1e4c SUBS r4,r1,#1
00034e b2e3 UXTB r3,r4
;;;1011 tmpreg1 |= (u32)tmpreg2 << 20;
000350 ea42ea42 ORR r2,r2,r3,LSL #20
;;;1012 /* Store the new register value */
;;;1013 ADCx->JSQR = tmpreg1;
000354 6382 STR r2,[r0,#0x38]
;;;1014 }
000356 bd10 POP {r4,pc}
ENDP
ADC_SetInjectedOffset PROC
;;;1038 /* Set the selected injected channel data offset */
;;;1039 *((u32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset;
000358 5042 STR r2,[r0,r1]
;;;1040 }
00035a 4770 BX lr
ENDP
ADC_GetInjectedConversionValue PROC
;;;1055 u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel)
;;;1056 {
00035c 4602 MOV r2,r0
;;;1057 /* Check the parameters */
;;;1058 assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
;;;1059
;;;1060 /* Returns the selected injected channel conversion data value */
;;;1061 return (u16) (*(u32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset)));
00035e 1850 ADDS r0,r2,r1
000360 6a80 LDR r0,[r0,#0x28]
000362 b280 UXTH r0,r0
;;;1062 }
000364 4770 BX lr
ENDP
ADC_AnalogWatchdogCmd PROC
;;;1089 {
;;;1090 u32 tmpreg = 0;
000366 2200 MOVS r2,#0
;;;1091
;;;1092 /* Check the parameters */
;;;1093 assert(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
;;;1094
;;;1095 /* Get the old register value */
;;;1096 tmpreg = ADCx->CR1;
000368 6842 LDR r2,[r0,#4]
;;;1097 /* Clear AWDEN, AWDENJ and AWDSGL bits */
;;;1098 tmpreg &= CR1_AWDMode_Reset;
00036a 4b23 LDR r3,|L1.1016|
00036c 401a ANDS r2,r2,r3
;;;1099 /* Set the analog watchdog enable mode */
;;;1100 tmpreg |= ADC_AnalogWatchdog;
00036e 430a ORRS r2,r2,r1
;;;1101 /* Store the new register value */
;;;1102 ADCx->CR1 = tmpreg;
000370 6042 STR r2,[r0,#4]
;;;1103 }
000372 4770 BX lr
ENDP
ADC_AnalogWatchdogThresholdsConfig PROC
;;;1123 /* Set the ADCx high threshold */
;;;1124 ADCx->HTR = HighThreshold;
000374 6241 STR r1,[r0,#0x24]
;;;1125 /* Set the ADCx low threshold */
;;;1126 ADCx->LTR = LowThreshold;
000376 6282 STR r2,[r0,#0x28]
;;;1127 }
000378 4770 BX lr
ENDP
ADC_AnalogWatchdogSingleChannelConfig PROC
;;;1158 {
;;;1159 u32 tmpreg = 0;
00037a 2200 MOVS r2,#0
;;;1160
;;;1161 /* Check the parameters */
;;;1162 assert(IS_ADC_CHANNEL(ADC_Channel));
;;;1163
;;;1164 /* Get the old register value */
;;;1165 tmpreg = ADCx->CR1;
00037c 6842 LDR r2,[r0,#4]
;;;1166 /* Clear the Analog watchdog channel select bits */
;;;1167 tmpreg &= CR1_AWDCH_Reset;
00037e f022f022 BIC r2,r2,#0x1f
;;;1168 /* Set the Analog watchdog channel */
;;;1169 tmpreg |= ADC_Channel;
000382 430a ORRS r2,r2,r1
;;;1170 /* Store the new register value */
;;;1171 ADCx->CR1 = tmpreg;
000384 6042 STR r2,[r0,#4]
;;;1172 }
000386 4770 BX lr
ENDP
ADC_TempSensorVrefintCmd PROC
;;;1186
;;;1187 if (NewState != DISABLE)
000388 b140 CBZ r0,|L1.924|
;;;1188 {
;;;1189 /* Enable the temperature sensor and Vrefint channel*/
;;;1190 ADC1->CR2 |= CR2_TSVREFE_Set;
00038a 491a LDR r1,|L1.1012|
00038c 3944 SUBS r1,r1,#0x44
00038e 6809 LDR r1,[r1,#0]
000390 f441f441 ORR r1,r1,#0x800000
000394 4a19 LDR r2,|L1.1020|
000396 f8c2f8c2 STR r1,[r2,#0x408]
00039a e007 B |L1.940|
|L1.924|
;;;1191 }
;;;1192 else
;;;1193 {
;;;1194 /* Disable the temperature sensor and Vrefint channel*/
;;;1195 ADC1->CR2 &= CR2_TSVREFE_Reset;
00039c 4915 LDR r1,|L1.1012|
00039e 3944 SUBS r1,r1,#0x44
0003a0 6809 LDR r1,[r1,#0]
0003a2 f421f421 BIC r1,r1,#0x800000
0003a6 4a15 LDR r2,|L1.1020|
0003a8 f8c2f8c2 STR r1,[r2,#0x408]
|L1.940|
;;;1196 }
;;;1197 }
0003ac 4770 BX lr
ENDP
ADC_GetFlagStatus PROC
;;;1213 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG)
;;;1214 {
0003ae 4602 MOV r2,r0
;;;1215 FlagStatus bitstatus = RESET;
0003b0 2000 MOVS r0,#0
;;;1216
;;;1217 /* Check the parameters */
;;;1218 assert(IS_ADC_GET_FLAG(ADC_FLAG));
;;;1219
;;;1220 /* Check the status of the specified ADC flag */
;;;1221 if ((ADCx->SR & ADC_FLAG) != (u8)RESET)
0003b2 6813 LDR r3,[r2,#0]
0003b4 420b TST r3,r1
0003b6 d001 BEQ |L1.956|
;;;1222 {
;;;1223 /* ADC_FLAG is set */
;;;1224 bitstatus = SET;
0003b8 2001 MOVS r0,#1
0003ba e000 B |L1.958|
|L1.956|
;;;1225 }
;;;1226 else
;;;1227 {
;;;1228 /* ADC_FLAG is reset */
;;;1229 bitstatus = RESET;
0003bc 2000 MOVS r0,#0
|L1.958|
;;;1230 }
;;;1231 /* Return the ADC_FLAG status */
;;;1232 return bitstatus;
;;;1233 }
0003be 4770 BX lr
ENDP
ADC_ClearFlag PROC
;;;1254 /* Clear the selected ADC flags */
;;;1255 ADCx->SR &= ~(u32)ADC_FLAG;
0003c0 6802 LDR r2,[r0,#0]
0003c2 438a BICS r2,r2,r1
0003c4 6002 STR r2,[r0,#0]
;;;1256 }
0003c6 4770 BX lr
ENDP
ADC_GetITStatus PROC
;;;1270 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT)
;;;1271 {
0003c8 b570 PUSH {r4-r6,lr}
0003ca 4602 MOV r2,r0
;;;1272 ITStatus bitstatus = RESET;
0003cc 2000 MOVS r0,#0
;;;1273 u8 itmask = 0, enablestatus;
0003ce 2300 MOVS r3,#0
;;;1274
;;;1275 /* Check the parameters */
;;;1276 assert(IS_ADC_GET_IT(ADC_IT));
;;;1277
;;;1278 /* Get the ADC IT index */
;;;1279 itmask = (u8)(ADC_IT >> 8);
0003d0 120b ASRS r3,r1,#8
;;;1280
;;;1281 /* Get the ADC_IT enable bit status */
;;;1282 enablestatus = (ADCx->CR1 & (u8)ADC_IT) ;
0003d2 6855 LDR r5,[r2,#4]
0003d4 b2ce UXTB r6,r1
0003d6 ea05ea05 AND r4,r5,r6
;;;1283
;;;1284 /* Check the status of the specified ADC interrupt */
;;;1285 if (((ADCx->SR & itmask) != (u8)RESET) && enablestatus)
0003da 6815 LDR r5,[r2,#0]
0003dc 421d TST r5,r3
0003de d00f BEQ |L1.1024|
0003e0 b174 CBZ r4,|L1.1024|
;;;1286 {
;;;1287 /* ADC_IT is set */
;;;1288 bitstatus = SET;
0003e2 2001 MOVS r0,#1
0003e4 e00d B |L1.1026|
0003e6 0000 DCW 0x0000
|L1.1000|
0003e8 bffedc00 DCD 0xbffedc00
|L1.1004|
0003ec fff0feff DCD 0xfff0feff
|L1.1008|
0003f0 fff1f7fd DCD 0xfff1f7fd
|L1.1012|
0003f4 4001244c DCD 0x4001244c
|L1.1016|
0003f8 ff3ffdff DCD 0xff3ffdff
|L1.1020|
0003fc 40012000 DCD 0x40012000
|L1.1024|
;;;1289 }
;;;1290 else
;;;1291 {
;;;1292 /* ADC_IT is reset */
;;;1293 bitstatus = RESET;
000400 2000 MOVS r0,#0
|L1.1026|
;;;1294 }
;;;1295 /* Return the ADC_IT status */
;;;1296 return bitstatus;
;;;1297 }
000402 bd70 POP {r4-r6,pc}
ENDP
ADC_ClearITPendingBit PROC
;;;1311 {
;;;1312 u8 itmask = 0;
000404 2200 MOVS r2,#0
;;;1313
;;;1314 /* Check the parameters */
;;;1315 assert(IS_ADC_IT(ADC_IT));
;;;1316
;;;1317 /* Get the ADC IT index */
;;;1318 itmask = (u8)(ADC_IT >> 8);
000406 120a ASRS r2,r1,#8
;;;1319
;;;1320 /* Clear the selected ADC interrupt pending bits */
;;;1321 ADCx->SR &= ~(u32)itmask;
000408 6803 LDR r3,[r0,#0]
00040a 4393 BICS r3,r3,r2
00040c 6003 STR r3,[r0,#0]
;;;1322 }
00040e 4770 BX lr
ENDP
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