stm32f10x_adc.txt

STM32 ARM 处理器的ADC采样源代码

                  ADC_StartCalibration PROC
;;;381      /* Enable the selected ADC calibration process */  
;;;382      ADCx->CR2 |= CR2_CAL_Set;
0000fa  6881              LDR      r1,[r0,#8]
0000fc  f041f041          ORR      r1,r1,#4
000100  6081              STR      r1,[r0,#8]
;;;383    }
000102  4770              BX       lr
                          ENDP

                  ADC_GetCalibrationStatus PROC
;;;392    FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
;;;393    {
000104  4601              MOV      r1,r0
;;;394      FlagStatus bitstatus = RESET;
000106  2000              MOVS     r0,#0
;;;395    
;;;396      /* Check the status of CAL bit */
;;;397      if ((ADCx->CR2 & CR2_CAL_Set) != (u16)RESET)
000108  688a              LDR      r2,[r1,#8]
00010a  f012f012          TST      r2,#4
00010e  d001              BEQ      |L1.276|
;;;398      {
;;;399        /* CAL bit is set: calibration on going */
;;;400        bitstatus = SET;
000110  2001              MOVS     r0,#1
000112  e000              B        |L1.278|
                  |L1.276|
;;;401      }
;;;402      else
;;;403      {
;;;404        /* CAL bit is reset: end of calibration */
;;;405        bitstatus = RESET;
000114  2000              MOVS     r0,#0
                  |L1.278|
;;;406      }
;;;407      /* Return the CAL bit status */
;;;408      return  bitstatus;
;;;409    }
000116  4770              BX       lr
                          ENDP

                  ADC_SoftwareStartConvCmd PROC
;;;424    
;;;425      if (NewState != DISABLE)
000118  b121              CBZ      r1,|L1.292|
;;;426      {
;;;427        /* Enable the selected ADC conversion on external event */
;;;428    	/* Starts the selected ADC conversion */
;;;429    	ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set;
00011a  6882              LDR      r2,[r0,#8]
00011c  f442f442          ORR      r2,r2,#0x500000
000120  6082              STR      r2,[r0,#8]
000122  e003              B        |L1.300|
                  |L1.292|
;;;430      }
;;;431      else
;;;432      {
;;;433        /* Stops the selected ADC conversion */
;;;434        /* Disable the selected ADC conversion on external event */
;;;435    	ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset;
000124  6882              LDR      r2,[r0,#8]
000126  f422f422          BIC      r2,r2,#0x500000
00012a  6082              STR      r2,[r0,#8]
                  |L1.300|
;;;436      }
;;;437    }
00012c  4770              BX       lr
                          ENDP

                  ADC_GetSoftwareStartConvStatus PROC
;;;446    FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
;;;447    {
00012e  4601              MOV      r1,r0
;;;448      FlagStatus bitstatus = RESET;
000130  2000              MOVS     r0,#0
;;;449    
;;;450      /* Check the status of SWSTRT bit */
;;;451      if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET)
000132  688a              LDR      r2,[r1,#8]
000134  f412f412          TST      r2,#0x400000
000138  d001              BEQ      |L1.318|
;;;452      {
;;;453        /* SWSTRT bit is set */
;;;454        bitstatus = SET;
00013a  2001              MOVS     r0,#1
00013c  e000              B        |L1.320|
                  |L1.318|
;;;455      }
;;;456      else
;;;457      {
;;;458        /* SWSTRT bit is reset */
;;;459        bitstatus = RESET;
00013e  2000              MOVS     r0,#0
                  |L1.320|
;;;460      }
;;;461      /* Return the SWSTRT bit status */
;;;462      return  bitstatus;
;;;463    }
000140  4770              BX       lr
                          ENDP

                  ADC_DiscModeChannelCountConfig PROC
;;;475    void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number)
;;;476    {
000142  b510              PUSH     {r4,lr}
;;;477      u32 tmpreg1 = 0;
000144  2200              MOVS     r2,#0
;;;478      u8 tmpreg2 = 0;
000146  2300              MOVS     r3,#0
;;;479    
;;;480      /* Check the parameters */
;;;481      assert(IS_ADC_REGULAR_DISC_NUMBER(Number));
;;;482    
;;;483      /* Get the old register value */
;;;484      tmpreg1 = ADCx->CR1;
000148  6842              LDR      r2,[r0,#4]
;;;485      /* Clear the old discontinuous mode channel count */
;;;486      tmpreg1 &= CR1_DISCNUM_Reset;
00014a  f422f422          BIC      r2,r2,#0xe000
;;;487      /* Set the discontinuous mode channel count */
;;;488      tmpreg2 = Number - 1;
00014e  1e4c              SUBS     r4,r1,#1
000150  b2e3              UXTB     r3,r4
;;;489      tmpreg1 |= ((u32)tmpreg2 << 13);
000152  ea42ea42          ORR      r2,r2,r3,LSL #13
;;;490      /* Store the new register value */
;;;491      ADCx->CR1 = tmpreg1;
000156  6042              STR      r2,[r0,#4]
;;;492    }
000158  bd10              POP      {r4,pc}
                          ENDP

                  ADC_DiscModeCmd PROC
;;;509    
;;;510      if (NewState != DISABLE)
00015a  b121              CBZ      r1,|L1.358|
;;;511      {
;;;512        /* Enable the selected ADC regular discontinuous mode */
;;;513        ADCx->CR1 |= CR1_DISCEN_Set;
00015c  6842              LDR      r2,[r0,#4]
00015e  f442f442          ORR      r2,r2,#0x800
000162  6042              STR      r2,[r0,#4]
000164  e003              B        |L1.366|
                  |L1.358|
;;;514      }
;;;515      else
;;;516      {
;;;517        /* Disable the selected ADC regular discontinuous mode */
;;;518        ADCx->CR1 &= CR1_DISCEN_Reset;
000166  6842              LDR      r2,[r0,#4]
000168  f422f422          BIC      r2,r2,#0x800
00016c  6042              STR      r2,[r0,#4]
                  |L1.366|
;;;519      }
;;;520    }
00016e  4770              BX       lr
                          ENDP

                  ADC_RegularChannelConfig PROC
;;;563    void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
;;;564    {
000170  b5f0              PUSH     {r4-r7,lr}
;;;565      u32 tmpreg1 = 0, tmpreg2 = 0;
000172  2400              MOVS     r4,#0
000174  2500              MOVS     r5,#0
;;;566    
;;;567      /* Check the parameters */
;;;568      assert(IS_ADC_CHANNEL(ADC_Channel));
;;;569      assert(IS_ADC_REGULAR_RANK(Rank));
;;;570      assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
;;;571    
;;;572      /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
;;;573      if (ADC_Channel > ADC_Channel_9)
000176  2909              CMP      r1,#9
000178  dd11              BLE      |L1.414|
;;;574      {
;;;575        /* Get the old register value */
;;;576        tmpreg1 = ADCx->SMPR1;
00017a  68c4              LDR      r4,[r0,#0xc]
;;;577        /* Calculate the mask to clear */
;;;578        tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
00017c  f1a1f1a1          SUB      r6,r1,#0xa
000180  eb06eb06          ADD      r7,r6,r6,LSL #1
000184  2607              MOVS     r6,#7
000186  fa06fa06          LSL      r5,r6,r7
;;;579        /* Clear the old discontinuous mode channel count */
;;;580        tmpreg1 &= ~tmpreg2;
00018a  43ac              BICS     r4,r4,r5
;;;581        /* Calculate the mask to set */
;;;582        tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
00018c  f1a1f1a1          SUB      r6,r1,#0xa
000190  eb06eb06          ADD      r6,r6,r6,LSL #1
000194  fa03fa03          LSL      r5,r3,r6
;;;583        /* Set the discontinuous mode channel count */
;;;584        tmpreg1 |= tmpreg2;
000198  432c              ORRS     r4,r4,r5
;;;585        /* Store the new register value */
;;;586        ADCx->SMPR1 = tmpreg1;
00019a  60c4              STR      r4,[r0,#0xc]
00019c  e00c              B        |L1.440|
                  |L1.414|
;;;587      }
;;;588      else /* ADC_Channel include in ADC_Channel_[0..9] */
;;;589      {
;;;590        /* Get the old register value */
;;;591        tmpreg1 = ADCx->SMPR2;
00019e  6904              LDR      r4,[r0,#0x10]
;;;592        /* Calculate the mask to clear */
;;;593        tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
0001a0  eb01eb01          ADD      r7,r1,r1,LSL #1
0001a4  2607              MOVS     r6,#7
0001a6  fa06fa06          LSL      r5,r6,r7
;;;594        /* Clear the old discontinuous mode channel count */
;;;595        tmpreg1 &= ~tmpreg2;
0001aa  43ac              BICS     r4,r4,r5
;;;596        /* Calculate the mask to set */
;;;597        tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
0001ac  eb01eb01          ADD      r6,r1,r1,LSL #1
0001b0  fa03fa03          LSL      r5,r3,r6
;;;598        /* Set the discontinuous mode channel count */
;;;599        tmpreg1 |= tmpreg2;
0001b4  432c              ORRS     r4,r4,r5
;;;600        /* Store the new register value */
;;;601        ADCx->SMPR2 = tmpreg1;
0001b6  6104              STR      r4,[r0,#0x10]
                  |L1.440|
;;;602      }
;;;603      /* For Rank 1 to 6 */
;;;604      if (Rank < 7)
0001b8  2a07              CMP      r2,#7
0001ba  da0f              BGE      |L1.476|
;;;605      {
;;;606        /* Get the old register value */
;;;607        tmpreg1 = ADCx->SQR3;
0001bc  6b44              LDR      r4,[r0,#0x34]
;;;608        /* Calculate the mask to clear */
;;;609        tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1));
0001be  1e56              SUBS     r6,r2,#1
0001c0  eb06eb06          ADD      r7,r6,r6,LSL #2
0001c4  261f              MOVS     r6,#0x1f
0001c6  fa06fa06          LSL      r5,r6,r7
;;;610        /* Clear the old SQx bits for the selected rank */
;;;611        tmpreg1 &= ~tmpreg2;
0001ca  43ac              BICS     r4,r4,r5
;;;612        /* Calculate the mask to set */
;;;613        tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
0001cc  1e56              SUBS     r6,r2,#1
0001ce  eb06eb06          ADD      r6,r6,r6,LSL #2
0001d2  fa01fa01          LSL      r5,r1,r6
;;;614        /* Set the SQx bits for the selected rank */
;;;615        tmpreg1 |= tmpreg2;
0001d6  432c              ORRS     r4,r4,r5
;;;616        /* Store the new register value */
;;;617        ADCx->SQR3 = tmpreg1;
0001d8  6344              STR      r4,[r0,#0x34]
0001da  e022              B        |L1.546|
                  |L1.476|
;;;618      }
;;;619      /* For Rank 7 to 12 */
;;;620      else if (Rank < 13)
0001dc  2a0d              CMP      r2,#0xd
0001de  da0f              BGE      |L1.512|
;;;621      {
;;;622        /* Get the old register value */
;;;623        tmpreg1 = ADCx->SQR2;
0001e0  6b04              LDR      r4,[r0,#0x30]
;;;624        /* Calculate the mask to clear */
;;;625        tmpreg2 = (u32)SQR2_SQ_Set << (5 * (Rank - 7));
0001e2  1fd6              SUBS     r6,r2,#7
0001e4  eb06eb06          ADD      r7,r6,r6,LSL #2
0001e8  261f              MOVS     r6,#0x1f
0001ea  fa06fa06          LSL      r5,r6,r7
;;;626        /* Clear the old SQx bits for the selected rank */
;;;627        tmpreg1 &= ~tmpreg2;
0001ee  43ac              BICS     r4,r4,r5
;;;628        /* Calculate the mask to set */
;;;629        tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));
0001f0  1fd6              SUBS     r6,r2,#7
0001f2  eb06eb06          ADD      r6,r6,r6,LSL #2
0001f6  fa01fa01          LSL      r5,r1,r6
;;;630        /* Set the SQx bits for the selected rank */
;;;631        tmpreg1 |= tmpreg2;
0001fa  432c              ORRS     r4,r4,r5
;;;632        /* Store the new register value */
;;;633        ADCx->SQR2 = tmpreg1;
0001fc  6304              STR      r4,[r0,#0x30]
0001fe  e010              B        |L1.546|
                  |L1.512|
;;;634      }
;;;635      /* For Rank 13 to 16 */
;;;636      else
;;;637      {
;;;638        /* Get the old register value */
;;;639        tmpreg1 = ADCx->SQR1;
000200  6ac4              LDR      r4,[r0,#0x2c]
;;;640        /* Calculate the mask to clear */
;;;641        tmpreg2 = (u32)SQR1_SQ_Set << (5 * (Rank - 13));
000202  f1a2f1a2          SUB      r6,r2,#0xd
000206  eb06eb06          ADD      r7,r6,r6,LSL #2
00020a  261f              MOVS     r6,#0x1f
00020c  fa06fa06          LSL      r5,r6,r7
;;;642        /* Clear the old SQx bits for the selected rank */
;;;643        tmpreg1 &= ~tmpreg2;
000210  43ac              BICS     r4,r4,r5