stm32f10x_adc.txt

STM32 ARM 处理器的ADC采样源代码

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 902] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\Obj\stm32f10x_adc.o --depend=..\Obj\stm32f10x_adc.d --device=DARMSTM -I..\..\..\..\..\INC\ST\STM32F10x -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_FLASH --omf_browse=..\Obj\stm32f10x_adc.crf ..\..\library\src\stm32f10x_adc.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  ADC_DeInit PROC
;;;127    void ADC_DeInit(ADC_TypeDef* ADCx)
;;;128    {
000000  b510              PUSH     {r4,lr}
000002  4604              MOV      r4,r0
;;;129      switch (*(u32*)&ADCx)
000004  48f8              LDR      r0,|L1.1000|
000006  1820              ADDS     r0,r4,r0
000008  d003              BEQ      |L1.18|
00000a  f5b0f5b0          CMP      r0,#0x400
00000e  d114              BNE      |L1.58|
000010  e009              B        |L1.38|
                  |L1.18|
;;;130      {
;;;131        case ADC1_BASE:
;;;132          /* Enable ADC1 reset state */
;;;133          RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
000012  2101              MOVS     r1,#1
000014  0248              LSLS     r0,r1,#9
000016  f7fff7ff          BL       RCC_APB2PeriphResetCmd
;;;134          /* Release ADC1 from reset state */
;;;135          RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
00001a  2100              MOVS     r1,#0
00001c  f44ff44f          MOV      r0,#0x200
000020  f7fff7ff          BL       RCC_APB2PeriphResetCmd
;;;136          break;
000024  e00a              B        |L1.60|
                  |L1.38|
;;;137        
;;;138        case ADC2_BASE:
;;;139          /* Enable ADC2 reset state */
;;;140          RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
000026  2101              MOVS     r1,#1
000028  0288              LSLS     r0,r1,#10
00002a  f7fff7ff          BL       RCC_APB2PeriphResetCmd
;;;141          /* Release ADC2 from reset state */
;;;142          RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
00002e  2100              MOVS     r1,#0
000030  f44ff44f          MOV      r0,#0x400
000034  f7fff7ff          BL       RCC_APB2PeriphResetCmd
;;;143          break;
000038  e000              B        |L1.60|
                  |L1.58|
;;;144    
;;;145        default:
;;;146          break;
00003a  bf00              NOP      
                  |L1.60|
00003c  bf00              NOP      
;;;147      }
;;;148    }
00003e  bd10              POP      {r4,pc}
                          ENDP

                  ADC_Init PROC
;;;161    void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
;;;162    {
000040  b530              PUSH     {r4,r5,lr}
;;;163      u32 tmpreg1 = 0;
000042  2200              MOVS     r2,#0
;;;164      u8 tmpreg2 = 0;
000044  2300              MOVS     r3,#0
;;;165    
;;;166      /* Check the parameters */
;;;167      assert(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
;;;168      assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
;;;169      assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));  		    
;;;170      assert(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));   
;;;171      assert(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
;;;172      assert(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
;;;173    
;;;174      /*---------------------------- ADCx CR1 Configuration -----------------*/
;;;175      /* Get the ADCx CR1 value */
;;;176      tmpreg1 = ADCx->CR1;
000046  6842              LDR      r2,[r0,#4]
;;;177      /* Clear DUALMODE and SCAN bits */
;;;178      tmpreg1 &= CR1_CLEAR_Mask;
000048  4ce8              LDR      r4,|L1.1004|
00004a  4022              ANDS     r2,r2,r4
;;;179      /* Configure ADCx: Dual mode and scan conversion mode */
;;;180      /* Set DUALMODE bits according to ADC_Mode value */
;;;181      /* Set SCAN bit according to ADC_ScanConvMode value */
;;;182      tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));
00004c  790d              LDRB     r5,[r1,#4]
00004e  680c              LDR      r4,[r1,#0]
000050  ea44ea44          ORR      r4,r4,r5,LSL #8
000054  4322              ORRS     r2,r2,r4
;;;183      /* Write to ADCx CR1 */
;;;184      ADCx->CR1 = tmpreg1;
000056  6042              STR      r2,[r0,#4]
;;;185    
;;;186      /*---------------------------- ADCx CR2 Configuration -----------------*/
;;;187      /* Get the ADCx CR2 value */
;;;188      tmpreg1 = ADCx->CR2;
000058  6882              LDR      r2,[r0,#8]
;;;189      /* Clear CONT, ALIGN and EXTTRIG bits */
;;;190      tmpreg1 &= CR2_CLEAR_Mask;
00005a  4ce5              LDR      r4,|L1.1008|
00005c  4022              ANDS     r2,r2,r4
;;;191      /* Configure ADCx: external trigger event and continuous conversion mode */
;;;192      /* Set ALIGN bit according to ADC_DataAlign value */
;;;193      /* Set EXTTRIG bits according to ADC_ExternalTrigConv value */
;;;194      /* Set CONT bit according to ADC_ContinuousConvMode value */
;;;195      tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
00005e  e9d1e9d1          LDRD     r5,r4,[r1,#8]
000062  432c              ORRS     r4,r4,r5
000064  794d              LDRB     r5,[r1,#5]
000066  ea44ea44          ORR      r4,r4,r5,LSL #1
00006a  4322              ORRS     r2,r2,r4
;;;196                ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));
;;;197      /* Write to ADCx CR2 */
;;;198      ADCx->CR2 = tmpreg1;
00006c  6082              STR      r2,[r0,#8]
;;;199    
;;;200      /*---------------------------- ADCx SQR1 Configuration -----------------*/
;;;201      /* Get the ADCx SQR1 value */
;;;202      tmpreg1 = ADCx->SQR1;
00006e  6ac2              LDR      r2,[r0,#0x2c]
;;;203      /* Clear L bits */
;;;204      tmpreg1 &= SQR1_CLEAR_Mask;
000070  f422f422          BIC      r2,r2,#0xf00000
;;;205      /* Configure ADCx: regular channel sequence length */
;;;206      /* Set L bits according to ADC_NbrOfChannel value */
;;;207      tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1);
000074  7c0c              LDRB     r4,[r1,#0x10]
000076  1e64              SUBS     r4,r4,#1
000078  431c              ORRS     r4,r4,r3
00007a  b2e3              UXTB     r3,r4
;;;208      tmpreg1 |= ((u32)tmpreg2 << 20);
00007c  ea42ea42          ORR      r2,r2,r3,LSL #20
;;;209      /* Write to ADCx SQR1 */
;;;210      ADCx->SQR1 = tmpreg1;
000080  62c2              STR      r2,[r0,#0x2c]
;;;211    }
000082  bd30              POP      {r4,r5,pc}
                          ENDP

                  ADC_StructInit PROC
;;;224      /* Initialize the ADC_Mode member */
;;;225      ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
000084  2100              MOVS     r1,#0
000086  6001              STR      r1,[r0,#0]
;;;226    
;;;227      /* initialize the ADC_ScanConvMode member */
;;;228      ADC_InitStruct->ADC_ScanConvMode = DISABLE;
000088  7101              STRB     r1,[r0,#4]
;;;229    
;;;230      /* Initialize the ADC_ContinuousConvMode member */
;;;231      ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
00008a  7141              STRB     r1,[r0,#5]
;;;232    
;;;233      /* Initialize the ADC_ExternalTrigConv member */
;;;234      ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
00008c  6081              STR      r1,[r0,#8]
;;;235    
;;;236      /* Initialize the ADC_DataAlign member */
;;;237      ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
00008e  60c1              STR      r1,[r0,#0xc]
;;;238    
;;;239      /* Initialize the ADC_NbrOfChannel member */
;;;240      ADC_InitStruct->ADC_NbrOfChannel = 1;
000090  2101              MOVS     r1,#1
000092  7401              STRB     r1,[r0,#0x10]
;;;241    }
000094  4770              BX       lr
                          ENDP

                  ADC_Cmd PROC
;;;256    
;;;257      if (NewState != DISABLE)
000096  b121              CBZ      r1,|L1.162|
;;;258      {
;;;259        /* Set the ADON bit to wake up the ADC from power down mode */
;;;260        ADCx->CR2 |= CR2_ADON_Set;
000098  6882              LDR      r2,[r0,#8]
00009a  f042f042          ORR      r2,r2,#1
00009e  6082              STR      r2,[r0,#8]
0000a0  e003              B        |L1.170|
                  |L1.162|
;;;261      }
;;;262      else
;;;263      {
;;;264        /* Disable the selected ADC peripheral */
;;;265        ADCx->CR2 &= CR2_ADON_Reset;
0000a2  6882              LDR      r2,[r0,#8]
0000a4  f022f022          BIC      r2,r2,#1
0000a8  6082              STR      r2,[r0,#8]
                  |L1.170|
;;;266      }
;;;267    }
0000aa  4770              BX       lr
                          ENDP

                  ADC_DMACmd PROC
;;;282    
;;;283      if (NewState != DISABLE)
0000ac  b121              CBZ      r1,|L1.184|
;;;284      {
;;;285        /* Enable the selected ADC DMA request */
;;;286        ADCx->CR2 |= CR2_DMA_Set;
0000ae  6882              LDR      r2,[r0,#8]
0000b0  f442f442          ORR      r2,r2,#0x100
0000b4  6082              STR      r2,[r0,#8]
0000b6  e004              B        |L1.194|
                  |L1.184|
;;;287      }
;;;288      else
;;;289      {
;;;290        /* Disable the selected ADC DMA request */
;;;291        ADCx->CR2 &= CR2_DMA_Reset;
0000b8  6882              LDR      r2,[r0,#8]
0000ba  f64ff64f          MOV      r3,#0xfeff
0000be  401a              ANDS     r2,r2,r3
0000c0  6082              STR      r2,[r0,#8]
                  |L1.194|
;;;292      }
;;;293    }
0000c2  4770              BX       lr
                          ENDP

                  ADC_ITConfig PROC
;;;310    void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState)
;;;311    {
0000c4  b510              PUSH     {r4,lr}
;;;312      u8 itmask = 0;
0000c6  2300              MOVS     r3,#0
;;;313    
;;;314      /* Check the parameters */
;;;315      assert(IS_FUNCTIONAL_STATE(NewState));
;;;316      assert(IS_ADC_IT(ADC_IT));
;;;317    
;;;318      /* Get the ADC IT index */
;;;319      itmask = (u8)ADC_IT;
0000c8  b2cb              UXTB     r3,r1
;;;320    
;;;321      if (NewState != DISABLE)
0000ca  b11a              CBZ      r2,|L1.212|
;;;322      {
;;;323        /* Enable the selected ADC interrupts */
;;;324        ADCx->CR1 |= itmask;
0000cc  6844              LDR      r4,[r0,#4]
0000ce  431c              ORRS     r4,r4,r3
0000d0  6044              STR      r4,[r0,#4]
0000d2  e002              B        |L1.218|
                  |L1.212|
;;;325      }
;;;326      else
;;;327      {
;;;328        /* Disable the selected ADC interrupts */
;;;329        ADCx->CR1 &= (~(u32)itmask);
0000d4  6844              LDR      r4,[r0,#4]
0000d6  439c              BICS     r4,r4,r3
0000d8  6044              STR      r4,[r0,#4]
                  |L1.218|
;;;330      }
;;;331    }
0000da  bd10              POP      {r4,pc}
                          ENDP

                  ADC_ResetCalibration PROC
;;;342      /* Resets the selected ADC calibartion registers */  
;;;343      ADCx->CR2 |= CR2_RSTCAL_Set;
0000dc  6881              LDR      r1,[r0,#8]
0000de  f041f041          ORR      r1,r1,#8
0000e2  6081              STR      r1,[r0,#8]
;;;344    }
0000e4  4770              BX       lr
                          ENDP

                  ADC_GetResetCalibrationStatus PROC
;;;353    FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
;;;354    {
0000e6  4601              MOV      r1,r0
;;;355      FlagStatus bitstatus = RESET;
0000e8  2000              MOVS     r0,#0
;;;356    
;;;357      /* Check the status of RSTCAL bit */
;;;358      if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u16)RESET)
0000ea  688a              LDR      r2,[r1,#8]
0000ec  f012f012          TST      r2,#8
0000f0  d001              BEQ      |L1.246|
;;;359      {
;;;360        /* RSTCAL bit is set */
;;;361        bitstatus = SET;
0000f2  2001              MOVS     r0,#1
0000f4  e000              B        |L1.248|
                  |L1.246|
;;;362      }
;;;363      else
;;;364      {
;;;365        /* RSTCAL bit is reset */
;;;366        bitstatus = RESET;
0000f6  2000              MOVS     r0,#0
                  |L1.248|
;;;367      }
;;;368      /* Return the RSTCAL bit status */
;;;369      return  bitstatus;
;;;370    }
0000f8  4770              BX       lr
                          ENDP