📄 stm32f10x_gpio.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 902] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\Obj\stm32f10x_gpio.o --depend=..\Obj\stm32f10x_gpio.d --device=DARMSTM -I..\..\..\..\..\INC\ST\STM32F10x -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_FLASH --omf_browse=..\Obj\stm32f10x_gpio.crf ..\..\library\src\stm32f10x_gpio.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
GPIO_DeInit PROC
;;;56 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
;;;57 {
000000 b510 PUSH {r4,lr}
000002 4604 MOV r4,r0
;;;58 switch (*(u32*)&GPIOx)
000004 49b0 LDR r1,|L1.712|
000006 1a60 SUBS r0,r4,r1
000008 428c CMP r4,r1
00000a d020 BEQ |L1.78|
00000c dc06 BGT |L1.28|
00000e 48af LDR r0,|L1.716|
000010 1820 ADDS r0,r4,r0
000012 d00a BEQ |L1.42|
000014 f5b0f5b0 CMP r0,#0x400
000018 d134 BNE |L1.132|
00001a e00f B |L1.60|
|L1.28|
00001c f5b0f5b0 CMP r0,#0x400
000020 d01e BEQ |L1.96|
000022 f5b0f5b0 CMP r0,#0x800
000026 d12d BNE |L1.132|
000028 e023 B |L1.114|
|L1.42|
;;;59 {
;;;60 case GPIOA_BASE:
;;;61 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
00002a 2101 MOVS r1,#1
00002c 2004 MOVS r0,#4
00002e f7fff7ff BL RCC_APB2PeriphResetCmd
;;;62 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
000032 2100 MOVS r1,#0
000034 2004 MOVS r0,#4
000036 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;63 break;
00003a e024 B |L1.134|
|L1.60|
;;;64
;;;65 case GPIOB_BASE:
;;;66 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
00003c 2101 MOVS r1,#1
00003e 2008 MOVS r0,#8
000040 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;67 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
000044 2100 MOVS r1,#0
000046 2008 MOVS r0,#8
000048 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;68 break;
00004c e01b B |L1.134|
|L1.78|
;;;69
;;;70 case GPIOC_BASE:
;;;71 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
00004e 2101 MOVS r1,#1
000050 2010 MOVS r0,#0x10
000052 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;72 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
000056 2100 MOVS r1,#0
000058 2010 MOVS r0,#0x10
00005a f7fff7ff BL RCC_APB2PeriphResetCmd
;;;73 break;
00005e e012 B |L1.134|
|L1.96|
;;;74
;;;75 case GPIOD_BASE:
;;;76 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
000060 2101 MOVS r1,#1
000062 2020 MOVS r0,#0x20
000064 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;77 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
000068 2100 MOVS r1,#0
00006a 2020 MOVS r0,#0x20
00006c f7fff7ff BL RCC_APB2PeriphResetCmd
;;;78 break;
000070 e009 B |L1.134|
|L1.114|
;;;79
;;;80 case GPIOE_BASE:
;;;81 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
000072 2101 MOVS r1,#1
000074 2040 MOVS r0,#0x40
000076 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;82 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
00007a 2100 MOVS r1,#0
00007c 2040 MOVS r0,#0x40
00007e f7fff7ff BL RCC_APB2PeriphResetCmd
;;;83 break;
000082 e000 B |L1.134|
|L1.132|
;;;84
;;;85 default:
;;;86 break;
000084 bf00 NOP
|L1.134|
000086 bf00 NOP
;;;87 }
;;;88 }
000088 bd10 POP {r4,pc}
ENDP
GPIO_AFIODeInit PROC
;;;99 void GPIO_AFIODeInit(void)
;;;100 {
00008a b510 PUSH {r4,lr}
;;;101 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
00008c 2101 MOVS r1,#1
00008e 4608 MOV r0,r1
000090 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;102 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
000094 2100 MOVS r1,#0
000096 2001 MOVS r0,#1
000098 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;103 }
00009c bd10 POP {r4,pc}
ENDP
GPIO_Init PROC
;;;116 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
;;;117 {
00009e b5f0 PUSH {r4-r7,lr}
;;;118 u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
0000a0 2200 MOVS r2,#0
0000a2 2300 MOVS r3,#0
0000a4 2400 MOVS r4,#0
0000a6 2500 MOVS r5,#0
;;;119 u32 tmpreg = 0x00, pinmask = 0x00;
0000a8 2600 MOVS r6,#0
0000aa 2700 MOVS r7,#0
;;;120
;;;121 /* Check the parameters */
;;;122 assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
;;;123 assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
;;;124
;;;125 /*---------------------------- GPIO Mode Configuration -----------------------*/
;;;126 currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
0000ac f891f891 LDRB r12,[r1,#3]
0000b0 f00cf00c AND r2,r12,#0xf
;;;127
;;;128 if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
0000b4 f891f891 LDRB r12,[r1,#3]
0000b8 f01cf01c TST r12,#0x10
0000bc d003 BEQ |L1.198|
;;;129 {
;;;130 /* Check the parameters */
;;;131 assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
;;;132 /* Output mode */
;;;133 currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
0000be f891f891 LDRB r12,[r1,#2]
0000c2 ea4cea4c ORR r2,r12,r2
|L1.198|
;;;134 }
;;;135
;;;136 /*---------------------------- GPIO CRL Configuration ------------------------*/
;;;137 /* Configure the eight low port pins */
;;;138 if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
0000c6 f8b1f8b1 LDRH r12,[r1,#0]
0000ca f01cf01c TST r12,#0xff
0000ce d031 BEQ |L1.308|
;;;139 {
;;;140 tmpreg = GPIOx->CRL;
0000d0 6806 LDR r6,[r0,#0]
;;;141
;;;142 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
0000d2 2400 MOVS r4,#0
0000d4 e02a B |L1.300|
|L1.214|
;;;143 {
;;;144 pos = ((u32)0x01) << pinpos;
0000d6 f04ff04f MOV r12,#1
0000da fa0cfa0c LSL r5,r12,r4
;;;145 /* Get the port pins position */
;;;146 currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
0000de f8b1f8b1 LDRH r12,[r1,#0]
0000e2 ea0cea0c AND r3,r12,r5
;;;147
;;;148 if (currentpin == pos)
0000e6 42ab CMP r3,r5
0000e8 d11f BNE |L1.298|
;;;149 {
;;;150 pos = pinpos << 2;
0000ea 00a5 LSLS r5,r4,#2
;;;151 /* Clear the corresponding low control register bits */
;;;152 pinmask = ((u32)0x0F) << pos;
0000ec f04ff04f MOV r12,#0xf
0000f0 fa0cfa0c LSL r7,r12,r5
;;;153 tmpreg &= ~pinmask;
0000f4 43be BICS r6,r6,r7
;;;154
;;;155 /* Write the mode configuration in the corresponding bits */
;;;156 tmpreg |= (currentmode << pos);
0000f6 fa02fa02 LSL r12,r2,r5
0000fa ea4cea4c ORR r6,r12,r6
;;;157
;;;158 /* Reset the corresponding ODR bit */
;;;159 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
0000fe f891f891 LDRB r12,[r1,#3]
000102 f1bcf1bc CMP r12,#0x28
000106 d105 BNE |L1.276|
;;;160 {
;;;161 GPIOx->BRR = (((u32)0x01) << pinpos);
000108 f04ff04f MOV r12,#1
00010c fa0cfa0c LSL r12,r12,r4
000110 f8c0f8c0 STR r12,[r0,#0x14]
|L1.276|
;;;162 }
;;;163 /* Set the corresponding ODR bit */
;;;164 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
000114 f891f891 LDRB r12,[r1,#3]
000118 f1bcf1bc CMP r12,#0x48
00011c d105 BNE |L1.298|
;;;165 {
;;;166 GPIOx->BSRR = (((u32)0x01) << pinpos);
00011e f04ff04f MOV r12,#1
000122 fa0cfa0c LSL r12,r12,r4
000126 f8c0f8c0 STR r12,[r0,#0x10]
|L1.298|
00012a 1c64 ADDS r4,r4,#1
|L1.300|
00012c 2c08 CMP r4,#8
00012e d3d2 BCC |L1.214|
;;;167 }
;;;168 }
;;;169 }
;;;170 GPIOx->CRL = tmpreg;
000130 6006 STR r6,[r0,#0]
;;;171 tmpreg = 0;
000132 2600 MOVS r6,#0
|L1.308|
;;;172 }
;;;173
;;;174 /*---------------------------- GPIO CRH Configuration ------------------------*/
;;;175 /* Configure the eight high port pins */
;;;176 if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
000134 f8b1f8b1 LDRH r12,[r1,#0]
000138 f1bcf1bc CMP r12,#0xff
00013c dd36 BLE |L1.428|
;;;177 {
;;;178 tmpreg = GPIOx->CRH;
00013e 6846 LDR r6,[r0,#4]
;;;179 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
000140 2400 MOVS r4,#0
000142 e030 B |L1.422|
|L1.324|
;;;180 {
;;;181 pos = (((u32)0x01) << (pinpos + 0x08));
000144 f104f104 ADD r12,r4,#8
000148 f04ff04f MOV lr,#1
00014c fa0efa0e LSL r5,lr,r12
;;;182 /* Get the port pins position */
;;;183 currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
000150 f8b1f8b1 LDRH r12,[r1,#0]
000154 ea0cea0c AND r3,r12,r5
;;;184 if (currentpin == pos)
000158 42ab CMP r3,r5
00015a d123 BNE |L1.420|
;;;185 {
;;;186 pos = pinpos << 2;
00015c 00a5 LSLS r5,r4,#2
;;;187 /* Clear the corresponding high control register bits */
;;;188 pinmask = ((u32)0x0F) << pos;
00015e f04ff04f MOV r12,#0xf
000162 fa0cfa0c LSL r7,r12,r5
;;;189 tmpreg &= ~pinmask;
000166 43be BICS r6,r6,r7
;;;190
;;;191 /* Write the mode configuration in the corresponding bits */
;;;192 tmpreg |= (currentmode << pos);
000168 fa02fa02 LSL r12,r2,r5
00016c ea4cea4c ORR r6,r12,r6
;;;193
;;;194 /* Reset the corresponding ODR bit */
;;;195 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
000170 f891f891 LDRB r12,[r1,#3]
000174 f1bcf1bc CMP r12,#0x28
000178 d107 BNE |L1.394|
;;;196 {
;;;197 GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
00017a f104f104 ADD r12,r4,#8
00017e f04ff04f MOV lr,#1
000182 fa0efa0e LSL lr,lr,r12
000186 f8c0f8c0 STR lr,[r0,#0x14]
|L1.394|
;;;198 }
;;;199 /* Set the corresponding ODR bit */
;;;200 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
00018a f891f891 LDRB r12,[r1,#3]
00018e f1bcf1bc CMP r12,#0x48
000192 d107 BNE |L1.420|
;;;201 {
;;;202 GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
000194 f104f104 ADD r12,r4,#8
000198 f04ff04f MOV lr,#1
00019c fa0efa0e LSL lr,lr,r12
0001a0 f8c0f8c0 STR lr,[r0,#0x10]
|L1.420|
0001a4 1c64 ADDS r4,r4,#1
|L1.422|
0001a6 2c08 CMP r4,#8
0001a8 d3cc BCC |L1.324|
;;;203 }
;;;204 }
;;;205 }
;;;206 GPIOx->CRH = tmpreg;
0001aa 6046 STR r6,[r0,#4]
|L1.428|
;;;207 }
;;;208 }
0001ac bdf0 POP {r4-r7,pc}
ENDP
GPIO_StructInit PROC
;;;220 /* Reset GPIO init structure parameters values */
;;;221 GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
0001ae f64ff64f MOV r1,#0xffff
0001b2 8001 STRH r1,[r0,#0]
;;;222 GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
0001b4 2102 MOVS r1,#2
0001b6 7081 STRB r1,[r0,#2]
;;;223 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
0001b8 2104 MOVS r1,#4
0001ba 70c1 STRB r1,[r0,#3]
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