dct2d_vhd.txt

the MDCT by the VHDL code

        
          if stage2_cnt_reg(0) = '0' then
            dcto <= STD_LOGIC_VECTOR(RESIZE
              (RESIZE(SIGNED(romedatao0),DA2_W) + 
              (RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') +
              (RESIZE(SIGNED(romedatao2),DA2_W-2) & "00") + 
              (RESIZE(SIGNED(romedatao3),DA2_W-3) & "000") +
              (RESIZE(SIGNED(romedatao4),DA2_W-4) & "0000") +
              (RESIZE(SIGNED(romedatao5),DA2_W-5) & "00000") +
              (RESIZE(SIGNED(romedatao6),DA2_W-6) & "000000") + 
              (RESIZE(SIGNED(romedatao7),DA2_W-7) & "0000000") +
              (RESIZE(SIGNED(romedatao8),DA2_W-8) & "00000000") +
              (RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") -
              (RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"),            
              DA2_W)(DA2_W-1 downto 12));
          else
            dcto <= STD_LOGIC_VECTOR(RESIZE
              (RESIZE(SIGNED(romodatao0),DA2_W) + 
              (RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') +
              (RESIZE(SIGNED(romodatao2),DA2_W-2) & "00") + 
              (RESIZE(SIGNED(romodatao3),DA2_W-3) & "000") +
              (RESIZE(SIGNED(romodatao4),DA2_W-4) & "0000") +
              (RESIZE(SIGNED(romodatao5),DA2_W-5) & "00000") +
              (RESIZE(SIGNED(romodatao6),DA2_W-6) & "000000") + 
              (RESIZE(SIGNED(romodatao7),DA2_W-7) & "0000000") +
              (RESIZE(SIGNED(romodatao8),DA2_W-8) & "00000000") +
              (RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") -
              (RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"),          
              DA2_W)(DA2_W-1 downto 12)); 
          end if;
          
          stage2_cnt_reg <= stage2_cnt_reg + 1;
          
          -- write RAM
          odv       <= '1';
    
          -- increment column counter
          col_reg   <= col_reg + 1;
          
          -- finished processing one input row
          if col_reg = N - 1 then
            row_reg         <= row_reg + 1;
          end if;  
        end if;
          
        if stage2_reg = '1' then
          stage2_cnt_reg <= (others => '0');
          col_reg        <= (0=>'1',others => '0');
        end if;
        --------------------------------
        
        ----------------------------------
        -- wait for new data
        ----------------------------------
        -- one of ram buffers has new data, process it
        if dataready = '1' and dataready_2_reg = '0'  then
          stage1_reg    <= '1';
          -- to account for 1T RAM delay, increment RAM address counter
          colram_reg    <= (others => '0');
          colr_reg      <= (0=>'1',others => '0');
          datareadyack  <= '1';
        end if;
        ----------------------------------
           
      end if;
    end if;
  end process;

  -- read precomputed MAC results from LUT
  romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(0) & 
           databuf_reg(1)(0) &
           databuf_reg(2)(0) &
           databuf_reg(3)(0);
  romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(1) & 
           databuf_reg(1)(1) &
           databuf_reg(2)(1) &
           databuf_reg(3)(1);
  romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(2) & 
           databuf_reg(1)(2) &
           databuf_reg(2)(2) &
           databuf_reg(3)(2);
  romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(3) & 
           databuf_reg(1)(3) &
           databuf_reg(2)(3) &
           databuf_reg(3)(3);          
  romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(4) & 
           databuf_reg(1)(4) &
           databuf_reg(2)(4) &
           databuf_reg(3)(4);                    
  romeaddro5  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(5) & 
           databuf_reg(1)(5) &
           databuf_reg(2)(5) &
           databuf_reg(3)(5); 
  romeaddro6  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(6) & 
           databuf_reg(1)(6) &
           databuf_reg(2)(6) &
           databuf_reg(3)(6);
  romeaddro7  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(7) & 
           databuf_reg(1)(7) &
           databuf_reg(2)(7) &
           databuf_reg(3)(7);
  romeaddro8  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(8) & 
           databuf_reg(1)(8) &
           databuf_reg(2)(8) &
           databuf_reg(3)(8); 
  romeaddro9  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(9) & 
           databuf_reg(1)(9) &
           databuf_reg(2)(9) &
           databuf_reg(3)(9);
  romeaddro10  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
           databuf_reg(0)(10) & 
           databuf_reg(1)(10) &
           databuf_reg(2)(10) &
           databuf_reg(3)(10);
  -- odd
  romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(0) & 
            databuf_reg(5)(0) &
            databuf_reg(6)(0) &
            databuf_reg(7)(0);
  romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(1) & 
            databuf_reg(5)(1) &
            databuf_reg(6)(1) &
            databuf_reg(7)(1);
  romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(2) & 
            databuf_reg(5)(2) &
            databuf_reg(6)(2) &
            databuf_reg(7)(2);
  romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(3) & 
            databuf_reg(5)(3) &
            databuf_reg(6)(3) &
            databuf_reg(7)(3);                   
  romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(4) & 
            databuf_reg(5)(4) &
            databuf_reg(6)(4) &
            databuf_reg(7)(4);
  romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(5) & 
            databuf_reg(5)(5) &
            databuf_reg(6)(5) &
            databuf_reg(7)(5);
  romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(6) & 
            databuf_reg(5)(6) &
            databuf_reg(6)(6) &
            databuf_reg(7)(6);
  romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(7) & 
            databuf_reg(5)(7) &
            databuf_reg(6)(7) &
            databuf_reg(7)(7);
  romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(8) & 
            databuf_reg(5)(8) &
            databuf_reg(6)(8) &
            databuf_reg(7)(8); 
  romoaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(9) & 
            databuf_reg(5)(9) &
            databuf_reg(6)(9) &
            databuf_reg(7)(9);
  romoaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & 
            databuf_reg(4)(10) & 
            databuf_reg(5)(10) &
            databuf_reg(6)(10) &
            databuf_reg(7)(10);
	
end RTL;
--------------------------------------------------------------------------------