divnfreq.v

来自「参数化分频器」· Verilog 代码 · 共 81 行

//--------------------------------------------------------------------------------------------------
//
// Title       : div5freq
// Design      : divFreq
// Author      : Allen Leng
// Company     : DEE
//
//-------------------------------------------------------------------------------------------------
//
// File        : div5freq.v
// Generated   : Fri Apr  8 16:51:29 2005
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description :   posedge and negedge using common counter "cnt"
//		parameter N is the double number of frequence division	
//-------------------------------------------------------------------------------------------------

`timescale 1ns / 100ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {div5freq}}
module div5freq ( rst ,clk ,clk5div );
parameter N=10; // double number of frequence division	

input rst ;
input clk ;

output clk5div ;

//}} End of automatically maintained section

// -- Enter your statements here -- //	 
reg Q1; // posedge 2:3 
reg Q2;	// negedge 2:3
reg [3:0]cnt;  // counter

assign clk5div=Q1 & Q2;


always @(posedge clk or posedge rst) 
begin	
	if(rst)	 
	  begin
 		Q1 <= 1'b0;
		cnt<= 4'd0;
	  end
 	else //if(posedge clk)		  
	 begin
		cnt<=cnt+1;
		if(cnt == (N/2-1))
			Q1 <= 1'b1;
		else if(cnt == (N-1))
			begin 
				Q1 <= 1'b0;
				cnt <= 4'd0;
			end	
	 end
end			

always @(negedge clk or posedge rst) 
begin	
	if(rst)	 
	  begin
 		Q2 <= 1'b0;	 
	  end
 	else //if(negedge clk)		  
	 begin 
		if( cnt ==  (N/2-1))
			Q2<=1'b1;
		else if( cnt == (N-1))
			Q2 <= 1'b0;			
	 end
end	


endmodule