📄 code.rpt
字号:
- 1 - F 05 OR2 s ! 0 4 0 1 ~4683~6
- 7 - F 10 OR2 s ! 0 4 0 1 ~4683~7
- 5 - F 01 OR2 s ! 0 4 0 1 ~4683~8
- 4 - F 07 OR2 s ! 0 4 0 1 ~4683~9
- 2 - F 10 AND2 s ! 0 4 0 2 ~4683~10
- 6 - F 15 OR2 s ! 0 4 0 1 ~4683~11
- 7 - F 13 OR2 s ! 0 4 0 1 ~4683~12
- 3 - F 22 OR2 s ! 0 4 0 1 ~4683~13
- 6 - F 17 OR2 s ! 0 4 0 1 ~4683~14
- 7 - F 15 AND2 s ! 0 4 0 1 ~4683~15
- 8 - F 08 OR2 s ! 0 4 0 1 ~4683~16
- 3 - F 11 OR2 s ! 0 4 0 1 ~4683~17
- 7 - F 02 OR2 s ! 0 4 0 1 ~4683~18
- 6 - F 06 OR2 s ! 0 4 0 1 ~4683~19
- 5 - F 08 AND2 s ! 0 4 0 1 ~4683~20
- 8 - F 15 AND2 0 4 0 17 :4683
- 1 - B 20 AND2 s ! 0 2 0 5 ~5471~1
- 8 - B 21 AND2 s ! 0 2 0 4 ~5471~2
- 8 - B 17 AND2 s 0 3 0 16 ~5471~3
- 4 - B 17 AND2 s ! 0 2 0 32 ~5471~4
- 6 - F 05 OR2 s 0 4 0 1 ~5507~1
- 5 - F 09 OR2 s 0 4 0 1 ~5543~1
- 4 - F 03 OR2 s 0 4 0 1 ~5579~1
- 4 - F 11 OR2 s ! 0 4 0 1 ~5615~1
- 8 - F 03 OR2 s 0 4 0 1 ~5651~1
- 4 - F 01 OR2 s 0 4 0 1 ~5687~1
- 8 - F 14 OR2 s 0 4 0 1 ~5723~1
- 3 - F 07 OR2 s ! 0 4 0 1 ~5759~1
- 2 - F 19 OR2 s 0 4 0 1 ~5795~1
- 4 - F 05 OR2 s 0 4 0 1 ~5831~1
- 7 - F 20 OR2 s 0 4 0 1 ~5867~1
- 8 - F 16 OR2 s ! 0 4 0 1 ~5903~1
- 3 - F 03 OR2 s 0 4 0 1 ~5939~1
- 2 - F 23 OR2 s 0 4 0 1 ~5975~1
- 5 - F 24 OR2 s 0 4 0 1 ~6011~1
- 6 - F 14 OR2 s 0 4 0 16 ~6047~1
- 6 - F 21 OR2 s ! 0 4 0 1 ~6047~2
- 4 - B 21 AND2 s 0 2 0 1 ~6047~3
- 1 - B 21 AND2 s ! 0 3 0 3 ~6083~1
- 2 - B 17 AND2 s ! 0 3 0 2 ~6083~2
- 6 - B 17 OR2 s 0 4 0 1 ~6083~3
- 7 - B 17 OR2 s 0 4 0 1 ~6083~4
- 3 - B 21 OR2 s 0 4 0 1 ~6119~1
- 6 - B 21 OR2 s 0 4 0 1 ~6119~2
- 7 - B 21 OR2 s 0 4 0 1 ~6119~3
- 2 - B 11 OR2 s 0 4 0 5 ~6155~1
- 3 - B 08 OR2 s 0 4 0 1 ~6155~2
- 8 - B 01 OR2 s 0 2 0 1 ~6155~3
- 1 - B 01 OR2 s 0 4 0 1 ~6155~4
- 7 - B 19 OR2 s ! 0 3 0 3 ~6178~1
- 5 - B 01 OR2 s 0 4 0 2 ~6191~1
- 6 - B 01 OR2 s 0 4 0 1 ~6191~2
- 6 - B 08 OR2 s 0 4 0 1 ~6191~3
- 3 - B 01 AND2 s 0 4 0 2 ~6191~4
- 4 - B 23 AND2 s ! 0 4 0 16 ~6767~1
- 8 - B 23 AND2 s ! 0 4 0 17 ~7343~1
- 5 - F 14 OR2 s 0 2 0 3 ~7352~1
- 1 - B 16 AND2 s ! 0 3 0 2 ~7379~1
- 3 - B 20 OR2 s 0 2 0 1 ~7379~2
- 3 - B 16 OR2 s 0 4 0 1 ~7379~3
- 2 - B 16 OR2 s 0 4 0 1 ~7379~4
- 4 - B 20 OR2 s 0 4 0 1 ~7379~5
- 5 - B 16 OR2 s 0 3 0 1 ~7415~1
- 4 - B 15 OR2 s 0 3 0 1 ~7415~2
- 5 - B 15 OR2 s 0 2 0 2 ~7415~3
- 6 - B 15 OR2 s 0 4 0 1 ~7415~4
- 8 - B 15 OR2 s 0 4 0 1 ~7415~5
- 5 - B 23 OR2 s 0 4 0 16 ~7991~1
- 4 - B 11 OR2 s 0 4 0 5 ~8135~1
- 1 - F 04 OR2 s 0 2 0 4 ~8135~2
- 5 - B 11 OR2 s 0 3 0 5 ~8279~1
- 1 - B 07 OR2 s 0 2 0 4 ~8279~2
- 1 - F 16 OR2 s 0 3 0 4 ~8423~1
- 8 - B 13 OR2 s 0 3 0 1 ~8459~1
- 1 - B 15 OR2 s 0 4 0 1 ~8459~2
- 1 - F 21 OR2 s 0 2 0 5 ~8603~1
- 3 - B 22 OR2 s 0 3 0 2 ~8610~1
- 7 - B 13 AND2 0 2 0 1 :8620
- 3 - B 14 OR2 s 0 4 0 1 ~8629~1
- 7 - B 20 OR2 ! 0 3 0 1 :8636
- 6 - B 14 OR2 s 0 4 0 1 ~8639~1
- 2 - B 22 OR2 0 4 0 1 :8640
- 3 - B 11 OR2 s 0 3 0 3 ~8647~1
- 5 - B 22 AND2 s 0 3 0 1 ~8647~2
- 7 - B 22 OR2 s 0 4 0 1 ~8647~3
- 8 - B 18 AND2 s 0 2 0 1 ~8652~1
- 5 - B 08 OR2 s 0 4 0 4 ~8674~1
- 3 - B 18 OR2 s 0 4 0 1 ~8674~2
- 8 - B 22 OR2 s 0 4 0 1 ~8674~3
- 3 - F 14 OR2 s 0 2 0 1 ~8674~4
- 5 - B 18 OR2 s 0 4 0 1 ~8674~5
- 6 - B 18 OR2 s 0 4 0 1 ~8674~6
- 7 - B 18 OR2 s 0 4 0 1 ~8674~7
- 2 - D 01 OR2 s ! 3 1 0 4 ~9423~1
- 7 - D 01 OR2 ! 2 2 0 2 :9455
- 5 - D 09 AND2 2 2 0 2 :9487
- 6 - D 09 AND2 2 2 0 2 :9519
- 8 - D 11 OR2 ! 2 2 0 2 :9551
- 5 - D 01 OR2 s 1 1 0 1 ~9583~1
- 7 - D 11 OR2 ! 2 2 0 2 :9583
- 1 - D 09 OR2 s 3 1 0 3 ~9615~1
- 2 - D 11 OR2 s 2 1 0 4 ~9615~2
- 8 - D 09 AND2 s ! 2 1 0 1 ~9615~3
- 5 - D 11 AND2 2 2 0 2 :9615
- 6 - D 11 AND2 2 2 0 2 :9647
- 2 - D 07 OR2 s 3 0 0 4 ~9679~1
- 2 - D 09 OR2 ! 2 2 0 2 :9679
- 4 - D 07 OR2 s 2 0 0 1 ~9711~1
- 5 - D 07 OR2 ! 2 2 0 2 :9711
- 2 - D 06 AND2 s ! 4 0 0 3 ~9775~1
- 1 - D 11 AND2 s ! 2 1 0 4 ~9775~2
- 7 - D 09 AND2 s ! 3 1 0 4 ~9775~3
- 3 - D 09 AND2 s ! 3 1 0 2 ~9775~4
- 4 - D 09 OR2 s 1 1 0 1 ~9775~5
- 1 - D 02 AND2 s ! 1 1 0 1 ~9775~6
- 6 - D 01 OR2 s 3 0 0 1 ~9775~7
- 8 - D 01 OR2 s 2 0 0 1 ~9775~8
- 1 - D 08 OR2 s ! 0 2 0 3 ~9780~1
- 3 - D 08 OR2 s ! 0 2 0 1 ~9780~2
- 5 - D 08 AND2 s 0 2 0 1 ~9780~3
- 6 - D 08 OR2 s ! 0 2 0 2 ~9807~1
- 3 - D 07 OR2 s ! 2 1 0 3 ~9828~1
- 3 - D 06 OR2 ! 3 1 0 1 :9843
- 3 - D 01 OR2 s ! 1 3 0 2 ~9844~1
- 4 - D 11 AND2 s ! 0 2 0 3 ~9856~1
- 8 - D 08 OR2 ! 0 4 0 1 :9856
- 1 - D 07 AND2 s ! 0 2 0 3 ~9868~1
- 4 - D 01 OR2 2 1 0 1 :9889
- 1 - D 01 OR2 0 4 0 1 :9903
- 3 - D 11 OR2 0 4 0 1 :9907
- 6 - D 07 OR2 0 4 0 1 :9921
- 1 - D 05 AND2 0 2 0 4 :10100
- 4 - B 08 OR2 ! 0 2 1 2 :10141
- 1 - B 05 AND2 0 2 0 1 :10211
- 2 - B 05 OR2 0 3 1 0 :10213
- 7 - B 11 OR2 0 3 1 0 :10234
- 4 - B 19 OR2 0 3 1 0 :10255
- 1 - B 19 OR2 0 3 1 0 :10276
- 7 - B 14 OR2 s 0 4 0 1 ~10297~1
- 5 - B 14 OR2 0 3 1 1 :10297
- 4 - B 14 AND2 ! 0 2 0 8 :10346
- 4 - D 06 OR2 3 1 0 4 :10560
- 5 - F 04 AND2 s 0 4 0 1 ~10569~1
- 4 - B 24 OR2 0 3 0 19 :10570
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\eda\45\k8\code\code.rpt
code
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 38/ 96( 39%) 12/ 48( 25%) 30/ 48( 62%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 14/ 96( 14%) 19/ 48( 39%) 3/ 48( 6%) 8/16( 50%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 50/ 96( 52%) 39/ 48( 81%) 31/ 48( 64%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 6/24( 25%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda\45\k8\code\code.rpt
code
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