📄 code.rpt
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** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
B5 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B7 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
B8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 6/22( 27%)
B11 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
B13 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 12/22( 54%)
B14 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
B15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 15/22( 68%)
B16 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 12/22( 54%)
B17 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 7/22( 31%)
B18 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 14/22( 63%)
B19 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
B20 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 7/22( 31%)
B21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 8/22( 36%)
B22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
B23 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
B24 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
C17 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 3/22( 13%)
C18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
D1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
D2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
D5 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 5/22( 22%)
D7 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
D8 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 1/2 1/2 10/22( 45%)
D9 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
D11 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
D13 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 1/22( 4%)
D21 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 3/22( 13%)
F1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
F2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
F3 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 12/22( 54%)
F4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
F5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
F6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
F7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
F8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 16/22( 72%)
F9 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 15/22( 68%)
F10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 11/22( 50%)
F11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 12/22( 54%)
F12 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 16/22( 72%)
F13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
F14 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
F15 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 18/22( 81%)
F16 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
F17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
F18 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
F19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 15/22( 68%)
F20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 14/22( 63%)
F21 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 11/22( 50%)
F22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
F23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
F24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 13/22( 59%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 19/96 ( 19%)
Total logic cells used: 378/1152 ( 32%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.59/4 ( 89%)
Total fan-in: 1360/4608 ( 29%)
Total input pins required: 16
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 378
Total flipflops required: 133
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 191/1152 ( 16%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 8 0 0 0 2 0 8 8 0 0 8 0 0 8 8 8 6 8 8 6 8 8 8 8 8 126/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2/0
D: 8 1 0 0 2 8 7 8 8 0 8 0 0 2 0 0 0 0 0 0 0 8 0 0 0 60/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 8 8 8 8 8 8 8 8 8 8 8 7 0 8 8 8 8 8 8 8 8 7 8 8 8 190/0
Total: 24 9 8 8 12 16 23 24 16 8 24 7 0 18 16 16 14 17 17 14 16 23 16 16 16 378/0
Device-Specific Information: f:\eda\45\k8\code\code.rpt
code
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT 0 0 0 5 chgcode
125 - - - -- INPUT 0 0 0 3 clear
55 - - - -- INPUT G 0 0 0 0 clk
70 - - - 05 INPUT 0 0 0 6 enter
119 - - - 07 INPUT 0 0 0 4 num0
21 - - D -- INPUT 0 0 0 4 num1
88 - - D -- INPUT 0 0 0 3 num2
23 - - D -- INPUT 0 0 0 6 num3
17 - - D -- INPUT 0 0 0 5 num4
18 - - D -- INPUT 0 0 0 5 num5
22 - - D -- INPUT 0 0 0 5 num6
56 - - - -- INPUT 0 0 0 5 num7
20 - - D -- INPUT 0 0 0 3 num8
19 - - D -- INPUT 0 0 0 6 num9
54 - - - -- INPUT G 0 0 0 1 res
124 - - - -- INPUT 0 0 0 6 user_admin
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\eda\45\k8\code\code.rpt
code
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
97 - - B -- OUTPUT 0 1 0 0 alarm
99 - - B -- OUTPUT 0 1 0 0 chgcode_ua
10 - - B -- OUTPUT 0 1 0 0 o_chgcode
96 - - B -- OUTPUT 0 1 0 0 openlock
122 - - - 13 OUTPUT 0 1 0 0 o_ua
135 - - - 19 OUTPUT 0 1 0 0 s_out0
9 - - B -- OUTPUT 0 1 0 0 s_out1
95 - - B -- OUTPUT 0 1 0 0 s_out2
98 - - B -- OUTPUT 0 1 0 0 s_out3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\eda\45\k8\code\code.rpt
code
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - D 21 AND2 0 3 0 3 |LPM_ADD_SUB:10387|addcore:adder|:125
- 6 - D 21 AND2 0 3 0 3 |LPM_ADD_SUB:10387|addcore:adder|:133
- 1 - C 18 SOFT s ! 1 0 0 64 res~1
- 6 - B 22 DFFE + 0 4 0 1 state~1
- 8 - B 08 AND2 s 0 3 0 2 state~2~2
- 7 - F 14 DFFE + 0 2 0 20 state~2
- 6 - B 23 DFFE + 0 4 0 38 state~3
- 4 - B 16 DFFE + 0 3 0 7 state~4
- 2 - B 18 DFFE + 0 3 0 11 state~5
- 3 - B 19 AND2 s 0 2 0 1 state~6~2
- 8 - B 11 AND2 s 0 4 0 1 state~6~3
- 6 - B 19 DFFE + 0 3 0 14 state~6
- 2 - B 23 DFFE + 0 3 0 11 state~7
- 1 - B 22 DFFE + 0 3 0 14 state~8
- 2 - B 14 DFFE + 0 2 0 7 state~9
- 1 - B 14 DFFE + 0 2 0 9 state~10
- 1 - B 13 DFFE + 0 3 0 15 state~11
- 5 - B 17 AND2 s 0 3 0 1 state~12~2
- 1 - B 18 DFFE + 0 4 0 16 state~12
- 8 - F 09 DFFE + 0 3 0 2 user_code15 (:26)
- 2 - F 09 DFFE + 0 3 0 2 user_code14 (:27)
- 7 - F 11 DFFE + 0 3 0 2 user_code13 (:28)
- 6 - F 11 DFFE + ! 0 3 0 2 user_code12 (:29)
- 5 - F 03 DFFE + 0 3 0 2 user_code11 (:30)
- 8 - F 02 DFFE + 0 3 0 2 user_code10 (:31)
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