sdprocess.vhd

这是用CPLD开发的读取绝对式编码器反馈的信号的代码

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity SDprocess is
	port(
		SD			:in std_logic;
		RQBUSY		:in std_logic;
		SFT			:in std_logic;
		CC			:in std_logic_vector(3 downto 0);

		ERR			:out std_logic;
		CRCE		:out std_logic;
		FORME		:out std_logic;
		SFOME		:out std_logic;
		CONTE		:out std_logic;
		RETRN		:out std_logic;
		RXBUSY		:out std_logic;
		SF,D0F,D1F,D2F,
		D3F,D4F,D5F,D6F,
		D7F,CRC,CD	:out std_logic_vector(7 downto 0);

		clk			:in std_logic;
		rstn		:in std_logic
	);
end SDprocess;

architecture MAIN of SDprocess is

component SDtiming
	port(
		SD		:in std_logic;
		RQBUSY	:in std_logic;
		RETRN	:in std_logic;
		SYNC	:in std_logic;
		SFT		:in std_logic;

		TIMING	:out std_logic_vector(8 downto 0);

		clk		:in std_logic;
		rstn	:in std_logic
	);
end component;

component BYTEread
	port(
		SD		:in std_logic;
		SFT		:in std_logic;

		RD		:out std_logic_vector(7 downto 0);

		clk		:in std_logic;
		rstn	:in std_logic
	);
end component;

component CRCGEN
	port(
		SD		:in std_logic;
		CLRN	:in	std_logic;
		SFT		:in std_logic;

		CRC		:out std_logic_vector(7 downto 0);

		clk		:in std_logic;
		rstn	:in std_logic
	);
end component;

signal SYNC,READ	:std_logic;
signal TIMING		:std_logic_vector(8 downto 0);
signal RB			:std_logic_vector(7 downto 0);
signal CRCC,CRCR	:std_logic;
signal CRCREG		:std_logic_vector(7 downto 0);
signal STRN,STPN	:std_logic;
signal FRAMELENGTH	:std_logic_vector(3 downto 0);
signal PERR			:std_logic;
signal ENDN			:std_logic;
signal P_SF,P_D0,P_D1,P_D2,
	P_D3,P_D4,P_D5,P_D6,
	P_D7,P_D8		:std_logic_vector(7 downto 0);
signal PPERR,PSTPE,PSTRE,
	PCRCE,ERRBUF	:std_logic;
signal CF			:std_logic_vector(7 downto 0);
signal RETRNbuf	:std_logic;
signal SYCCHK,CRCCHK,STRCHK,
	STPCHK,PARCHK,ERRCHK,
	LOAD			:std_logic;

begin

	SDTIM	:SDtiming 	port map (SD,RQBUSY,RETRNbuf,SYNC,SFT,TIMING,clk,rstn);
	SDB		:BYTEread 	port map (SD,READ,RB,clk,rstn);
	CRCG	:CRCGEN		port map(RB(7),CRCR,CRCC,CRCREG,clk,rstn);

	process(SYCCHK,RB(7 downto 5))begin
		if(SYCCHK='1' and RB(7 downto 5)/="010")then SYNC<='1';else SYNC<='0';end if;
	end process;

-- TIMECHART --
	process(TIMING,SFT)
	variable STRN,STPN	:std_logic;
	variable TIMINGU6	:std_logic_vector(8 downto 3);
	begin
		TIMINGU6:=TIMING(8 downto 3);
		if(TIMING<="000000100")then CRCR<='0';else CRCR<='1';end if;
		if(TIMING(1 downto 0)="01" and SFT='1')then READ<='1';else READ<='0';end if;
		if( TIMINGU6="000000" or TIMINGU6="000101" or TIMINGU6="001010" or
			TIMINGU6="001111" or TIMINGU6="010100" or TIMINGU6="011001" or
			TIMINGU6="011110" or TIMINGU6="100011" or TIMINGU6="101000" or
			TIMINGU6="101101" or TIMINGU6="110010")then STRN:='1';else STRN:='0';end if;
		if( TIMINGU6="000100" or TIMINGU6="001001" or TIMINGU6="001110" or
			TIMINGU6="010011" or TIMINGU6="011000" or TIMINGU6="011101" or
			TIMINGU6="100010" or TIMINGU6="100111" or TIMINGU6="101100" or
			TIMINGU6="110001" or TIMINGU6="110110")then STPN:='1';else STPN:='0';end if;
		if(	(STRN='0' and TIMING(2 downto 0)="011")or
		 	(STPN='0' and TIMING(2 downto 0)="111")or
			(TIMING="000000011"))then CRCC<='1';else CRCC<='0';end if;
		if(STRN='1' and TIMING(2 downto 0)="011")then STRCHK<='1';else STRCHK<='0';end if;
		if(STPN='1' and TIMING(2 downto 0)="111")then STPCHK<='1';else STPCHK<='1';end if;
		if(TIMING="000100101")then PARCHK<='1';else PARCHK<='0';end if;
		if(TIMING="000001111")then SYCCHK<='1';else SYCCHK<='0';end if;
	end process;

	process(clk,rstn)begin
		if(rstn='0')then
			RXBUSY<='1';
		elsif(clk='1' and clk' event)then
			if(TIMING<"000011000")then RXBUSY<='1';else RXBUSY<='0';end if;
		end if;
	end process;

-- get ID and frame length --
	process(clk,rstn)
	variable PARITY :std_logic;
	variable DID	:std_logic_vector(3 downto 0);
	begin
		if(rstn='0')then
			FRAMELENGTH<=(others=>'0');
		elsif(clk='1' and clk' event)then
			if(TIMING="000100011")then
				CF<=RB;
				DID:=RB(6 downto 3);
				case DID is
					when x"2"=> FRAMELENGTH<=x"0";
					when x"3"=> FRAMELENGTH<=x"7";
					when x"4"=> FRAMELENGTH<=x"3";
					when x"5"=> FRAMELENGTH<=x"5";
					when x"6"=> FRAMELENGTH<=x"0";
					when x"9"=> FRAMELENGTH<=x"3";
					when x"a"=> FRAMELENGTH<=x"5";
					when x"b"=> FRAMELENGTH<=x"3";
					when x"d"=> FRAMELENGTH<=x"0";
					when x"e"=> FRAMELENGTH<=x"3";
					when x"f"=> FRAMELENGTH<=x"3";
					when others=> FRAMELENGTH<=x"2";
				end case;
				PARITY:='0';
				for i in 3 to 7 loop
					PARITY:=PARITY xor RB(i);
				end loop;
				PERR<=PARITY;
			end if;
		end if;
	end process;

	process(FRAMELENGTH,TIMING,ERRBUF)
	variable ENDN	:std_logic;
	variable TIMINGU6	:std_logic_vector(8 downto 3);
	begin
		TIMINGU6:=TIMING(8 downto 3);
		if	(FRAMELENGTH=x"0" and TIMING="010011101") or
			(FRAMELENGTH=x"2" and TIMING="011101101") or
			(FRAMELENGTH=x"3" and TIMING="100010101") or
			(FRAMELENGTH=x"5" and TIMING="101100101") or
			(FRAMELENGTH=x"7" and TIMING="110110101")then CRCCHK<='1';else CRCCHK<='0';end if;
		if	(FRAMELENGTH=x"0" and TIMINGU6="010100") or
			(FRAMELENGTH=x"2" and TIMINGU6="011110") or
			(FRAMELENGTH=x"3" and TIMINGU6="100011") or
			(FRAMELENGTH=x"5" and TIMINGU6="101101") or
			(FRAMELENGTH=x"7" and TIMINGU6="110111")then ENDN:='1';else ENDN:='0';end if;
		if(ENDN='1' and TIMING(2 downto 0)="001")then ERRCHK<='1';else ERRCHK<='0';end if;
		if(ENDN='1' and TIMING(2 downto 0)="011" and ERRBUF='0')then LOAD<='1';else LOAD<='0';end if;
		if(ENDN='1' and TIMING(2 downto 0)="101")then RETRNbuf<='1';else RETRNbuf<='0';end if;
	end process;

	process(clk,rstn)begin
		if(rstn='0')then
			P_SF<=(others=>'0');
			P_D0<=(others=>'0');
			P_D1<=(others=>'0');
			P_D2<=(others=>'0');
			P_D3<=(others=>'0');
			P_D4<=(others=>'0');
			P_D5<=(others=>'0');
			P_D6<=(others=>'0');
			P_D7<=(others=>'0');
			P_D8<=(others=>'0');
			SF<=(others=>'0');
			D0F<=(others=>'0');
			D1F<=(others=>'0');
			D2F<=(others=>'0');
			D3F<=(others=>'0');
			D4F<=(others=>'0');
			D5F<=(others=>'0');
			D6F<=(others=>'0');
			D7F<=(others=>'0');
			CRC<=(others=>'0');
		elsif(clk='1' and clk' event)then
			if(CRCR='0')then
				P_SF<=(others=>'0');
				P_D0<=(others=>'0');
				P_D1<=(others=>'0');
				P_D2<=(others=>'0');
				P_D3<=(others=>'0');
				P_D4<=(others=>'0');
				P_D5<=(others=>'0');
				P_D6<=(others=>'0');
				P_D7<=(others=>'0');
				P_D8<=(others=>'0');
			else
				if(TIMING="001001011")then P_SF<=RB;end if;
				if(TIMING="001110011")then P_D0<=RB;end if;
				if(TIMING="010011011")then P_D1<=RB;end if;
				if(TIMING="011000011")then P_D2<=RB;end if;
				if(TIMING="011101011")then P_D3<=RB;end if;
				if(TIMING="100010011")then P_D4<=RB;end if;
				if(TIMING="100111011")then P_D5<=RB;end if;
				if(TIMING="101100011")then P_D6<=RB;end if;
				if(TIMING="110001011")then P_D7<=RB;end if;
				if(TIMING="110110011")then P_D8<=RB;end if;
			end if;
			if(LOAD='1')then
				SF<=P_SF;
				D0F<=P_D0;
				D1F<=P_D1;
				D2F<=P_D2;
				D3F<=P_D3;
				D4F<=P_D4;
				D5F<=P_D5;
				D6F<=P_D6;
				D7F<=P_D7;
				CRC<=P_D8;
			end if;
		end if;
	end process;

-- Error process --
	process(clk,rstn)begin
		if(rstn='0')then
			CRCE<='0';
			FORME<='0';
			SFOME<='0';
			CONTE<='0';
			ERRBUF<='0';
			PCRCE<='0';
			PSTPE<='0';
			PSTRE<='0';
			PPERR<='0';
		elsif(clk='1' and clk' event)then
			if(ERRCHK='1')then
				CRCE<=PCRCE;
				FORME<=(PSTRE or PSTPE);
				SFOME<=(PSTRE or PSTPE);
				CONTE<=PPERR;
				ERRBUF<=(PCRCE or PSTRE or PSTPE or PPERR);
			end if;
			if(CRCCHK='1')then
				if(CRCREG="00000000")then PCRCE<='0';else PCRCE<='1';end if;
			end if;
			if(STRCHK='1')then
				PSTRE<=RB(7);
			end if;
			if(STPCHK='1')then
				PSTPE<=not RB(7);
			end if;
			if(PARCHK='1')then
				PPERR<=PERR;
			end if;
		end if;
	end process;

	ERR<=ERRBUF;
	RETRN<=RETRNbuf;
	CD(7 downto 3)<=CF(7 downto 3);
	CD(2)<='0';
	CD(0)<=ERRBUF;

	process(CC(3 downto 0),CF(6 downto 3))begin
		if(CF(6 downto 3)=CC(3 downto 0))then CD(1)<='0';else CD(1)<='1';end if;
	end process;
end MAIN;