timeoutdetect.vhd

这是用CPLD开发的读取绝对式编码器反馈的信号的代码

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity TIMEOUTdetect is

	generic(
		SYS_CLK		: integer	:=20;	--system clock[MHz]
		RQ_TOUT		: integer	:=200	--timeout[us]
		);

	port(
		SDbusy	:in	std_logic;
		RQRET	:in std_logic;

		TIMEOUT	:out std_logic;

		clk		:in	std_logic;
		rstn	:in std_logic
	);

end TIMEOUTdetect;

architecture MAIN of TIMEOUTdetect is

signal	SDWAIT	:std_logic;
signal	TOTIMER	:integer range 0 to (SYS_CLK*RQ_TOUT);
signal	TObuf	:std_logic;

begin
	process(clk,rstn)begin
		if(rstn='0')then
			SDWAIT<='0';
			TOTIMER<=0;
		elsif(clk='1' and clk' event)then
			if(SDBUSY='1' and TObuf='0' and (RQRET='1' or SDWAIT='1'))then
				SDWAIT<='1';
			else
				SDWAIT<='0';
			end if;

			if((TOTIMER=(SYS_CLK*RQ_TOUT) or TObuf='1')and SDBUSY='1')then
				TObuf<='1';else TObuf<='0';
			end if;

			if(SDWAIT='0')then
				TOTIMER<=0;
			else
				TOTIMER<=TOTIMER+1;
			end if;

		end if;
	end process;
	TIMEOUT<=TObuf;
end MAIN;