📄 ccd.map.rpt
字号:
Analysis & Synthesis report for CCD
Tue Sep 23 15:44:02 2008
Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Registers Removed During Synthesis
8. Source assignments for lpm_counter:V_COUNTER_rtl_0
9. Source assignments for lpm_counter:H_COUNTER_rtl_1
10. Source assignments for lpm_counter:H_COUNTER_CLR_rtl_2
11. Source assignments for lpm_counter:V_COUNTER_CLR_rtl_3
12. Parameter Settings for Inferred Entity Instance: lpm_counter:V_COUNTER_rtl_0
13. Parameter Settings for Inferred Entity Instance: lpm_counter:H_COUNTER_rtl_1
14. Parameter Settings for Inferred Entity Instance: lpm_counter:H_COUNTER_CLR_rtl_2
15. Parameter Settings for Inferred Entity Instance: lpm_counter:V_COUNTER_CLR_rtl_3
16. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 23 15:44:02 2008 ;
; Quartus II Version ; 7.1 Build 178 06/25/2007 SP 1 SJ Full Version ;
; Revision Name ; CCD ;
; Top-level Entity Name ; CCD ;
; Family ; MAX7000S ;
; Total macrocells ; 66 ;
; Total pins ; 16 ;
+-----------------------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-10 ; ;
; Top-level entity name ; CCD ; CCD ;
; Family name ; MAX7000S ; Stratix ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------------------+-----------------+---------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------------------+
; CCD.vhd ; yes ; User VHDL File ; D:/MyProject/2米4摄谱仪狭缝监视系统/CCD_VHDL/CCD.vhd ;
; lpm_counter.tdf ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal71.inc ; yes ; Megafunction ; d:/program files/altera/quartus/libraries/megafunctions/aglobal71.inc ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 66 ;
; Total registers ; 58 ;
; I/O pins ; 16 ;
; Shareable expanders ; 8 ;
; Parallel expanders ; 5 ;
; Maximum fan-out node ; STATE[2] ;
; Maximum fan-out ; 45 ;
; Total fan-out ; 546 ;
; Average fan-out ; 6.07 ;
+----------------------+----------------------+
+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------+------------+------+--------------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+--------------------------------------+------------+------+--------------------------------------+--------------+
; |CCD ; 66 ; 16 ; |CCD ; work ;
; |lpm_counter:H_COUNTER_CLR_rtl_2| ; 4 ; 0 ; |CCD|lpm_counter:H_COUNTER_CLR_rtl_2 ; work ;
; |lpm_counter:H_COUNTER_rtl_1| ; 9 ; 0 ; |CCD|lpm_counter:H_COUNTER_rtl_1 ; work ;
; |lpm_counter:V_COUNTER_CLR_rtl_3| ; 10 ; 0 ; |CCD|lpm_counter:V_COUNTER_CLR_rtl_3 ; work ;
; |lpm_counter:V_COUNTER_rtl_0| ; 9 ; 0 ; |CCD|lpm_counter:V_COUNTER_rtl_0 ; work ;
+--------------------------------------+------------+------+--------------------------------------+--------------+
+---------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+-----------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+-----------------------+
; SRG1~reg0 ; Merged with SRG2~reg0 ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+-----------------------+
+----------------------------------------------------+
; Source assignments for lpm_counter:V_COUNTER_rtl_0 ;
+---------------------------+-------+------+---------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+---------+
; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ;
+---------------------------+-------+------+---------+
+----------------------------------------------------+
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -