i2c_fpga.fit.eqn

利用I2c读取E2prom Verilog 代码

D1_inner_state.seventh = DFFEAS(D1_inner_state.seventh_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1_inner_state.fifth is i2c:inst4|inner_state.fifth at LC_X8_Y8_N4
--operation mode is normal

D1_inner_state.fifth_lut_out = D1_main_state.10 & (D1L97 # D1_main_state.01 & D1L100) # !D1_main_state.10 & D1_main_state.01 & (D1L100);
D1_inner_state.fifth = DFFEAS(D1_inner_state.fifth_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1_inner_state.third is i2c:inst4|inner_state.third at LC_X8_Y5_N5
--operation mode is normal

D1_inner_state.third_lut_out = D1_main_state.01 & (D1L106 # D1_main_state.10 & D1L103) # !D1_main_state.01 & D1_main_state.10 & (D1L103);
D1_inner_state.third = DFFEAS(D1_inner_state.third_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1_inner_state.first is i2c:inst4|inner_state.first at LC_X9_Y5_N4
--operation mode is normal

D1_inner_state.first_lut_out = D1_main_state.01 & (D1L111 # D1L108 & D1_main_state.10) # !D1_main_state.01 & D1L108 & D1_main_state.10;
D1_inner_state.first = DFFEAS(D1_inner_state.first_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1L19 is i2c:inst4|Select~12538 at LC_X8_Y8_N6
--operation mode is normal

D1L19 = !D1_inner_state.fifth & (!D1_inner_state.first & !D1_inner_state.third);


--D1_inner_state.sixth is i2c:inst4|inner_state.sixth at LC_X10_Y8_N6
--operation mode is normal

D1_inner_state.sixth_lut_out = D1L114 & (D1_main_state.10 # D1_main_state.01 & D1L117) # !D1L114 & D1_main_state.01 & (D1L117);
D1_inner_state.sixth = DFFEAS(D1_inner_state.sixth_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1_inner_state.fourth is i2c:inst4|inner_state.fourth at LC_X10_Y8_N3
--operation mode is normal

D1_inner_state.fourth_lut_out = D1_main_state.01 & (D1L123 # D1L120 & D1_main_state.10) # !D1_main_state.01 & D1L120 & D1_main_state.10;
D1_inner_state.fourth = DFFEAS(D1_inner_state.fourth_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1L20 is i2c:inst4|Select~12539 at LC_X10_Y8_N9
--operation mode is normal

D1L20 = !D1_inner_state.sixth & !D1_inner_state.fourth;


--D1_inner_state.second is i2c:inst4|inner_state.second at LC_X8_Y5_N8
--operation mode is normal

D1_inner_state.second_lut_out = D1_main_state.01 & (D1L129 # D1_main_state.10 & D1L126) # !D1_main_state.01 & D1_main_state.10 & (D1L126);
D1_inner_state.second = DFFEAS(D1_inner_state.second_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1_inner_state.eighth is i2c:inst4|inner_state.eighth at LC_X8_Y7_N4
--operation mode is normal

D1_inner_state.eighth_lut_out = D1_main_state.01 & (D1L135 # D1_main_state.10 & D1L132) # !D1_main_state.01 & D1_main_state.10 & D1L132;
D1_inner_state.eighth = DFFEAS(D1_inner_state.eighth_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1L21 is i2c:inst4|Select~12540 at LC_X8_Y7_N0
--operation mode is normal

D1L21 = D1_inner_state.stop # D1_inner_state.eighth # !D1_inner_state.start & !D1_phase1;


--D1L22 is i2c:inst4|Select~12541 at LC_X9_Y9_N6
--operation mode is normal

D1L22 = D1_inner_state.second # D1L21 & D1_sda_buf;


--D1L23 is i2c:inst4|Select~12542 at LC_X9_Y9_N9
--operation mode is normal

D1L23 = D1_phase3 & (D1L22) # !D1_phase3 & D1_sda_buf & (D1L22 # !D1L137);


--D1L24 is i2c:inst4|Select~12543 at LC_X8_Y9_N5
--operation mode is normal

D1L24 = !D1_i2c_state.ini & (D1L23 # D1L136);


--D1L25 is i2c:inst4|Select~12544 at LC_X10_Y6_N7
--operation mode is normal

D1L25 = D1_sda_buf & (D1_i2c_state.read_data # D1_i2c_state.read_ini) # !D1_main_state.01;


--D1L26 is i2c:inst4|Select~12545 at LC_X7_Y9_N8
--operation mode is normal

D1L26 = !D1_phase3 & D1L18;


--D1L27 is i2c:inst4|Select~12546 at LC_X8_Y8_N7
--operation mode is normal

D1L27 = !D1_inner_state.second & !D1_inner_state.seventh & D1L19;


--D1L28 is i2c:inst4|Select~12547 at LC_X8_Y8_N3
--operation mode is normal

D1L28 = D1_inner_state.start & !D1_inner_state.eighth & !D1_inner_state.stop;


--D1L29 is i2c:inst4|Select~12548 at LC_X8_Y8_N9
--operation mode is normal

D1L29 = D1_phase3 & (D1L138) # !D1_phase3 & (D1L27 & D1L138 # !D1_sda_buf);


--D1L30 is i2c:inst4|Select~12549 at LC_X7_Y9_N7
--operation mode is normal

D1L30 = D1L25 # D1_i2c_state.sendaddr & (D1L26 # !D1L29);


--D1L31 is i2c:inst4|Select~12550 at LC_X7_Y9_N6
--operation mode is normal

D1L31 = D1_sda_buf & (D1_inner_state.eighth # D1_inner_state.stop # !D1_inner_state.start);


--D1L32 is i2c:inst4|Select~12551 at LC_X10_Y8_N1
--operation mode is normal

D1L32 = D1_inner_state.sixth & (D1_writeData_reg[1] # D1_writeData_reg[3] & D1_inner_state.fourth) # !D1_inner_state.sixth & D1_writeData_reg[3] & (D1_inner_state.fourth);


--D1L33 is i2c:inst4|Select~12552 at LC_X8_Y8_N1
--operation mode is normal

D1L33 = D1_inner_state.fifth & (D1_writeData_reg[2] # D1_inner_state.seventh & D1_writeData_reg[0]) # !D1_inner_state.fifth & (D1_inner_state.seventh & D1_writeData_reg[0]);


--D1L34 is i2c:inst4|Select~12553 at LC_X7_Y9_N9
--operation mode is normal

D1L34 = D1L31 # D1_phase3 & (D1L32 # D1L33);


--D1L35 is i2c:inst4|Select~12554 at LC_X7_Y9_N2
--operation mode is normal

D1L35 = D1_phase1 & (D1_inner_state.stop # D1L18) # !D1_phase1 & !D1_phase3 & (D1L18);


--D1L345 is i2c:inst4|sda_buf~139 at LC_X8_Y9_N6
--operation mode is normal

D1L345 = !D1_phase3 & D1_sda_buf;


--D1L36 is i2c:inst4|Select~12555 at LC_X8_Y8_N0
--operation mode is normal

D1L36 = !D1_inner_state.seventh & !D1_inner_state.second & D1L19 & D1L20;


--D1L37 is i2c:inst4|Select~12556 at LC_X7_Y9_N0
--operation mode is normal

D1L37 = D1L34 # D1L35 # !D1L36 & D1L345;


--D1L38 is i2c:inst4|Select~12557 at LC_X7_Y9_N3
--operation mode is normal

D1L38 = D1L30 # D1L24 # D1_i2c_state.write_data & D1L37;


--D1L346 is i2c:inst4|sda_buf~140 at LC_X7_Y8_N4
--operation mode is normal

D1L346 = D1_phase0 & (A1L6) # !D1_phase0 & (D1_sda_buf);


--D1L39 is i2c:inst4|Select~12558 at LC_X7_Y8_N5
--operation mode is normal

D1L39 = D1_inner_state.ack & (D1_phase3 # D1L346) # !D1L29;


--D1L40 is i2c:inst4|Select~12559 at LC_X7_Y8_N3
--operation mode is normal

D1L40 = D1_sda_buf & (D1_inner_state.stop # !D1_inner_state.start) # !D1_sda_buf & D1_phase1 & D1_inner_state.stop;


--D1L41 is i2c:inst4|Select~12560 at LC_X7_Y8_N7
--operation mode is normal

D1L41 = D1L139 # D1L346 & (D1_inner_state.eighth # !D1L36);


--D1L42 is i2c:inst4|Select~12561 at LC_X7_Y8_N8
--operation mode is normal

D1L42 = D1_i2c_state.sendaddr & (D1L39 # D1_i2c_state.read_data & D1L41) # !D1_i2c_state.sendaddr & D1_i2c_state.read_data & (D1L41);


--D1L43 is i2c:inst4|Select~12562 at LC_X8_Y9_N9
--operation mode is normal

D1L43 = D1_sda_buf & D1_i2c_state.write_data # !D1_main_state.10;


--D1L44 is i2c:inst4|Select~12563 at LC_X8_Y9_N7
--operation mode is normal

D1L44 = D1_sda_buf & (D1_inner_state.second # D1_inner_state.seventh) # !D1_sda_buf & D1_phase3 & (D1_inner_state.second # D1_inner_state.seventh);


--D1L45 is i2c:inst4|Select~12564 at LC_X8_Y9_N8
--operation mode is normal

D1L45 = D1L17 # D1L44 # D1_sda_buf & D1L21;


--D1L46 is i2c:inst4|Select~12565 at LC_X8_Y9_N2
--operation mode is normal

D1L46 = D1L18 # D1L345 & (!D1L19 # !D1L20);


--D1L47 is i2c:inst4|Select~12566 at LC_X8_Y9_N3
--operation mode is normal

D1L47 = D1L43 # D1_i2c_state.read_ini & (D1L45 # D1L46);


--D1L48 is i2c:inst4|Select~12567 at LC_X7_Y9_N4
--operation mode is normal

D1L48 = D1L38 & (D1L47 # D1L24 # D1L42);


--D1L12 is i2c:inst4|Equal~734 at LC_X6_Y7_N9
--operation mode is normal

D1L12 = !D1_clk_div[0] & !D1_clk_div[7] & D1_clk_div[3];


--D1L13 is i2c:inst4|Equal~735 at LC_X6_Y7_N3
--operation mode is normal

D1L13 = !D1_clk_div[2] & (!D1_clk_div[5]);


--D1L49 is i2c:inst4|Select~12568 at LC_X8_Y6_N4
--operation mode is normal

D1L49 = D1_inner_state.ack & D1_i2c_state.sendaddr & D1_phase3;


--D1L50 is i2c:inst4|Select~12569 at LC_X8_Y6_N1
--operation mode is normal

D1L50 = D1_inner_state.ack & D1_phase3;


--D1L51 is i2c:inst4|Select~12570 at LC_X9_Y7_N1
--operation mode is normal

D1L51 = D1_main_state.10 & (D1_inner_state.stop # D1L50 & D1_i2c_state.read_data);


--D1L52 is i2c:inst4|Select~12571 at LC_X9_Y7_N4
--operation mode is normal

D1L52 = D1_i2c_state.write_data & D1_inner_state.ack;


--D1L53 is i2c:inst4|Select~12572 at LC_X9_Y7_N5
--operation mode is normal

D1L53 = !D1_phase1 & D1L52 & (D1_phase3 # D1_inner_state.stop);


--C1_inst4 is delay_reset_block:inst2|inst4 at LC_X14_Y6_N6
--operation mode is normal

C1_inst4 = !G1_cout # !write;


--D1L305 is i2c:inst4|main_state~2373 at LC_X11_Y7_N9
--operation mode is normal

D1L305 = !D1_inner_state.stop # !D1_phase3;


--D1L306 is i2c:inst4|main_state~2374 at LC_X11_Y7_N3
--operation mode is normal

D1L306 = D1_i2c_state.read_data & (D1L305) # !D1_i2c_state.read_data & (!D1_phase1 # !D1_sda_buf);


--D1L307 is i2c:inst4|main_state~2375 at LC_X11_Y7_N4
--operation mode is normal

D1L307 = D1_main_state.10 & (D1L306 # !D1_i2c_state.read_data & !D1L299);


--D1L308 is i2c:inst4|main_state~2376 at LC_X11_Y7_N8
--operation mode is normal

D1L308 = !D1_main_state.00 & (!D1L6 & D1L303);


--D1L54 is i2c:inst4|Select~12573 at LC_X10_Y6_N4
--operation mode is normal

D1L54 = D1_phase3 & (D1_inner_state.ack & D1_i2c_state.read_ini);


--D1L309 is i2c:inst4|main_state~2378 at LC_X11_Y7_N2
--operation mode is normal

D1L309 = D1_inner_state.stop & (D1_i2c_state.write_data & (D1_phase3) # !D1_i2c_state.write_data & D1_sda_buf) # !D1_inner_state.stop & D1_sda_buf;


--D1L310 is i2c:inst4|main_state~2379 at LC_X10_Y7_N9
--operation mode is normal

D1L310 = !D1_i2c_state.read_ini & !D1_i2c_state.read_data & D1_inner_state.ack & D1_phase1;


--D1L311 is i2c:inst4|main_state~2380 at LC_X10_Y7_N1
--operation mode is normal

D1L311 = D1_i2c_state.write_data & !D1_inner_state.ack & D1_phase3;


--D1L312 is i2c:inst4|main_state~2381 at LC_X11_Y7_N6
--operation mode is normal

D1L312 = !D1L315 & D1_main_state.01 & (!D1L309 # !D1L310);


--D1L55 is i2c:inst4|Select~12574 at LC_X9_Y6_N5
--operation mode is normal

D1L55 = D1_inner_state.ack & D1_phase3 & !D1_i2c_state.write_data & !D1_i2c_state.read_data;


--D1L56 is i2c:inst4|Select~12575 at LC_X9_Y6_N7
--operation mode is normal

D1L56 = D1L49 # D1_i2c_state.read_ini & !D1L55;


--D1L332 is i2c:inst4|reduce_nor~89 at LC_X8_Y7_N7
--operation mode is normal

D1L332 = D1_inner_state.start & (!D1_inner_state.stop);


--D1L57 is i2c:inst4|Select~12576 at LC_X8_Y7_N9
--operation mode is normal

D1L57 = D1_phase3 & (D1L332 & D1_inner_state.eighth # !D1L332 & (D1_inner_state.ack)) # !D1_phase3 & (D1_inner_state.ack);


--D1L58 is i2c:inst4|Select~12577 at LC_X8_Y6_N5
--operation mode is normal

D1L58 = D1_phase3 & D1_inner_state.eighth # !D1_phase3 & (D1_inner_state.ack);


--D1L59 is i2c:inst4|Select~12578 at LC_X6_Y8_N7
--operation mode is normal

D1L59 = D1_i2c_state.read_data # D1_i2c_state.sendaddr;


--D1L60 is i2c:inst4|Select~12579 at LC_X8_Y6_N7
--operation mode is normal

D1L60 = D1_i2c_state.write_data & D1_inner_state.ack # !D1_i2c_state.write_data & (D1L140);


--D1L61 is i2c:inst4|Select~12580 at LC_X7_Y6_N2
--operation mode is normal

D1L61 = D1_inner_state.eighth # D1L332 & (!D1_phase1 # !D1_inner_state.ack);


--D1L62 is i2c:inst4|Select~12581 at LC_X7_Y6_N5
--operation mode is normal

D1L62 = D1_i2c_state.sendaddr # D1_i2c_state.write_data & D1L61;


--D1L63 is i2c:inst4|Select~12582 at LC_X7_Y6_N3
--operation mode is normal

D1L63 = D1_i2c_state.ini & D1_i2c_state.write_data & (D1L61) # !D1_i2c_state.ini & (D1_i2c_state.write_data & D1L61 # !D1_i2c_state.sendaddr);


--D1L64 is i2c:inst4|Select~12583 at LC_X7_Y6_N8
--operation mode is normal

D1L64 = D1L62 & (D1L63) # !D1L62 & (D1L63 & (D1L58) # !D1L63 & D1_inner_state.ack);


--D1L285 is i2c:inst4|inner_state~924 at LC_X6_Y6_N6
--operation mode is normal

D1L285 = !D1_phase3 & D1_inner_state.ack;


--D1L65 is i2c:inst4|Select~12584 at LC_X7_Y6_N9
--operation mode is normal